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| author | Robert Norton <rmn30@cam.ac.uk> | 2019-07-19 11:21:40 +0100 |
|---|---|---|
| committer | Robert Norton <rmn30@cam.ac.uk> | 2019-07-19 11:38:25 +0100 |
| commit | ad348876ca17529c4d7fe2f3d2ec227f9f3026e1 (patch) | |
| tree | 4359244f3e810470c646e8463dfc2b0b7661f433 /doc/figs/riscvspecdeps.tex | |
| parent | 9735f8824f8a58debf49ac15c6bb1232f3ade499 (diff) | |
| download | sail-riscv-master-cleanup.zip sail-riscv-master-cleanup.tar.gz sail-riscv-master-cleanup.tar.bz2 | |
Add a new pc access function to get the architectural PC: on CHERI this is not what is in the PC register because the architectural PC is the offset of PCC and the PC register stores the absolute PC (at present -- may review this decision in future). This allows fix for AUIPC and RVFI reported PC.master-cleanup
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