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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-09-11 16:31:53 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-09-11 16:44:45 -0700 |
| commit | b9c136aac38b2afae1ddc9b205975e6002a60846 (patch) | |
| tree | 36cac3f644212b74d7ca20716fa5e5cf9f845c79 /doc/ReadingGuide.md | |
| parent | a999811942f542099765cd5024954960c4a6c7f9 (diff) | |
| download | sail-riscv-b9c136aac38b2afae1ddc9b205975e6002a60846.zip sail-riscv-b9c136aac38b2afae1ddc9b205975e6002a60846.tar.gz sail-riscv-b9c136aac38b2afae1ddc9b205975e6002a60846.tar.bz2 | |
Update the docs for the virtual memory and exception-code extensions.
Diffstat (limited to 'doc/ReadingGuide.md')
| -rw-r--r-- | doc/ReadingGuide.md | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/doc/ReadingGuide.md b/doc/ReadingGuide.md index 50f865d..1e77a33 100644 --- a/doc/ReadingGuide.md +++ b/doc/ReadingGuide.md @@ -77,10 +77,11 @@ such as the platform memory map. are used in the weak memory concurrency model. - The `riscv_vmem_*.sail` files describe the S-mode address - translation. `riscv_vmem_common.sail` contains the definitions and - processing of the page-table entries and their various permission - and status bits. `riscv_vmem_sv32.sail`, `riscv_vmem_sv39.sail`, - and `riscv_vmem_sv48.sail` contain the specifications for the + translation. `riscv_vmem_types` and `riscv_vmem_common.sail` + contain the definitions and processing of the page-table entries and + their various permission and status bits. `riscv_types_ext`, + `riscv_vmem_sv32.sail`, `riscv_vmem_sv39.sail`, and + `riscv_vmem_sv48.sail` contain the specifications for the corresponding page-table walks, and `riscv_vmem_rv32.sail` and `riscv_vmem_rv64.sail` describe the top-level address translation for the corresponding architectures. |