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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-10 11:23:18 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-10 11:23:18 -0700 |
| commit | 2b0984ab49d48651e6daff0bcc3c37b8b49e2602 (patch) | |
| tree | c8758bc43029fdc2b525e6bba8ff6a60dc222a7c /doc/ReadingGuide.md | |
| parent | 374a1e221c32a2856e31dfcd44abf539cc07a425 (diff) | |
| download | sail-riscv-2b0984ab49d48651e6daff0bcc3c37b8b49e2602.zip sail-riscv-2b0984ab49d48651e6daff0bcc3c37b8b49e2602.tar.gz sail-riscv-2b0984ab49d48651e6daff0bcc3c37b8b49e2602.tar.bz2 | |
Update docs.
Diffstat (limited to 'doc/ReadingGuide.md')
| -rw-r--r-- | doc/ReadingGuide.md | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/doc/ReadingGuide.md b/doc/ReadingGuide.md index 5c7e656..ad09cf0 100644 --- a/doc/ReadingGuide.md +++ b/doc/ReadingGuide.md @@ -25,13 +25,21 @@ The model contains the following Sail modules in the `model` directory: register type is separately defined in `riscv_reg_type.sail` so that extensions of the model can redefine it if required. +- `riscv_regs.sail` contains the base register file, where each + register is defined as having the `regtype` type defined in + `riscv_reg_type.sail`. + +- `riscv_pc_access.sail` defines functions to access and modify the + program counter. + - `riscv_sys_regs.sail` describes the privileged architectural state, viz. M-mode and S-mode CSRs, and contains helpers to interpret their content, such as WLRL and WARL fields. `riscv_sys_control.sail` describes interrupt and exception delegation and dispatch, and the handling of privilege transitions. `riscv_sys_exceptions.sail` defines the handling of the addresses involved in exception - handling. + handling. `riscv_sync_exception.sail` describes the structure used + to capture the architectural information for an exception. Since WLRL and WARL fields are intended to capture platform-specific functionality, future versions of the model might separate their |