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authorPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-05-10 13:37:31 -0700
committerPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-05-10 13:37:31 -0700
commit360685d92fc5e027f14ad105786c7663f3a482a5 (patch)
treeb42d60c13b4e5f432afa935852b698c6156df4b9 /doc/ExtendingGuide.md
parent860f3dba67d45b4b6461b8af9edacaa3f9182fdb (diff)
parent2b0984ab49d48651e6daff0bcc3c37b8b49e2602 (diff)
downloadsail-riscv-inst_extensions.zip
sail-riscv-inst_extensions.tar.gz
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Merge branch 'master' into inst_extensionsinst_extensions
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diff --git a/doc/ExtendingGuide.md b/doc/ExtendingGuide.md
index 4533b8b..82a418d 100644
--- a/doc/ExtendingGuide.md
+++ b/doc/ExtendingGuide.md
@@ -33,6 +33,15 @@ existing definitions for privilege levels and exceptions in
`riscv_types.sail`, and modifying the exception handling and privilege
transition functions in `riscv_sys_control.sail`.
+Modifying exception handling
+----------------------------
+
+An extension that needs to interact closely with exception handling
+may need to capture additional information at the time of an
+exception. This is supported using the `ext` field in the
+`sync_exception` type in `riscv_sync_exception.sail`, which is where
+the extension can store this information.
+
Adding low-level platform functionality
---------------------------------------
@@ -91,6 +100,13 @@ The handling of the memory addresses involved during exception
handling can be extending using the interface defined in
`riscv_sys_exceptions.sail`.
+Checking and transforming the program counter
+---------------------------------------------
+
+An extension might want to similarly check and transform accesses to
+the program counter. This is supported by supplying implementations
+of the functions defined in `riscv_pc_access.sail`.
+
Adding new instructions
-----------------------