Generalize the previous commit to handle hardwired misa.c.

5 files changed, 20 insertions, 4 deletions

diff --git a/c_emulator/riscv_platform.c b/c_emulator/riscv_platform.c
index d1b1f6e..dcc5766 100644
--- a/c_emulator/riscv_platform.c
+++ b/c_emulator/riscv_platform.c
@@ -9,6 +9,11 @@
 static mach_bits reservation = 0;
 static bool reservation_valid = false;
 
+bool sys_enable_rvc(unit u)
+{ return rv_enable_rvc; }
+bool sys_enable_writable_misa(unit u)
+{ return rv_enable_writable_misa; }
+
 bool plat_enable_dirty_update(unit u)
 { return rv_enable_dirty_update; }
 
diff --git a/c_emulator/riscv_platform.h b/c_emulator/riscv_platform.h
index 728555e..31f2807 100644
--- a/c_emulator/riscv_platform.h
+++ b/c_emulator/riscv_platform.h
@@ -1,6 +1,9 @@
 #pragma once
 #include "sail.h"
 
+bool sys_enable_rvc(unit);
+bool sys_enable_writable_misa(unit);
+
 bool plat_enable_dirty_update(unit);
 bool plat_enable_misaligned_access(unit);
 bool plat_mtval_has_illegal_inst_bits(unit);
diff --git a/c_emulator/riscv_platform_impl.c b/c_emulator/riscv_platform_impl.c
index ed32979..5894fc9 100644
--- a/c_emulator/riscv_platform_impl.c
+++ b/c_emulator/riscv_platform_impl.c
@@ -3,6 +3,8 @@
 #include <stdio.h>
 
 /* Settings of the platform implementation, with common defaults. */
+bool rv_enable_rvc                  = true;
+bool rv_enable_writable_misa        = true;
 
 bool rv_enable_dirty_update         = false;
 bool rv_enable_misaligned           = false;
diff --git a/c_emulator/riscv_platform_impl.h b/c_emulator/riscv_platform_impl.h
index 2e59fd8..cf3bc30 100644
--- a/c_emulator/riscv_platform_impl.h
+++ b/c_emulator/riscv_platform_impl.h
@@ -7,6 +7,8 @@
 
 #define DEFAULT_RSTVEC     0x00001000
 
+extern bool rv_enable_rvc;
+extern bool rv_enable_writable_misa;
 extern bool rv_enable_dirty_update;
 extern bool rv_enable_misaligned;
 extern bool rv_mtval_has_illegal_inst_bits;
diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c
index 7be7fce..1176400 100644
--- a/c_emulator/riscv_sim.c
+++ b/c_emulator/riscv_sim.c
@@ -45,7 +45,6 @@ const char *RV32ISA = "RV32IMAC";
 #define CSR_MIP 0x344
 
 static bool do_dump_dts = false;
-static bool disable_compressed = false;
 static bool do_show_times = false;
 struct tv_spike_t *s = NULL;
 char *term_log = NULL;
@@ -78,6 +77,7 @@ static struct option options[] = {
   {"enable-misaligned",           no_argument,       0, 'm'},
   {"ram-size",                    required_argument, 0, 'z'},
   {"disable-compressed",          no_argument,       0, 'C'},
+  {"disable-writable-misa",       no_argument,       0, 'I'},
   {"mtval-has-illegal-inst-bits", no_argument,       0, 'i'},
   {"dump-dts",                    no_argument,       0, 's'},
   {"device-tree-blob",            required_argument, 0, 'b'},
@@ -187,7 +187,10 @@ char *process_args(int argc, char **argv)
       rv_enable_misaligned = true;
       break;
     case 'C':
-      disable_compressed = true;
+      rv_enable_rvc = false;
+      break;
+    case 'I':
+      rv_enable_writable_misa = false;
       break;
     case 'i':
       rv_mtval_has_illegal_inst_bits = true;
@@ -424,8 +427,9 @@ void init_sail(uint64_t elf_entry)
   } else
 #endif
   init_sail_reset_vector(elf_entry);
-  if (disable_compressed)
-    z_set_Misa_C(&zmisa, 0);
+
+  // this is probably unnecessary now; remove
+  if (!rv_enable_rvc) z_set_Misa_C(&zmisa, 0);
 }
 
 int init_check(struct tv_spike_t *s)