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| author | Martin Berger <contact@martinfriedrichberger.net> | 2024-04-30 09:33:57 +0100 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2024-05-07 19:56:04 -0500 |
| commit | 5c55b5bb6f6d69dc3ff58a2ce9b25c4e582f6e88 (patch) | |
| tree | 87652b9baf9ecae2b7920ba14606d05c5a210bd3 /c_emulator | |
| parent | 418cf128bf212058dfc6a9a3d952edf2a61ce920 (diff) | |
| download | sail-riscv-5c55b5bb6f6d69dc3ff58a2ce9b25c4e582f6e88.zip sail-riscv-5c55b5bb6f6d69dc3ff58a2ce9b25c4e582f6e88.tar.gz sail-riscv-5c55b5bb6f6d69dc3ff58a2ce9b25c4e582f6e88.tar.bz2 | |
Add Svinval extension.
These changes add the "Svinval" Standard Extension for Fine-Grained
Address-Translation Cache Invalidation, Version 1.0 to the sail-riscv
model.
This extension defines five new instructions: SINVAL.VMA,
SFENCE.W.INVAL, SFENCE.INVAL.IR, HINVAL.VVMA, HINVAL.GVMA.
HINVAL.VVMA & HINVAL.GVMA are omitted since they build on the
Hypervisor Extension which is yet to be included in the model.
SFENCE.W.INVAL & SFENCE.INVAL.IR are treated as nops pending
integration of the coherency model (rmem) with sail.
The specification says that SINVAL.VMA behaves just as SFENCE.VMA,
except there are additional ordering constraints with respect to the
new SFENCE.W.INVAL & SFENCE.INVAL.IR instructions. Since these are
nops, we can treat SINVAL.VMA as if it were SFENCE.VMA.
Co-authored-by: Kristin Barber <kristinbarber@google.com>
Diffstat (limited to 'c_emulator')
| -rw-r--r-- | c_emulator/riscv_sim.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c index ee90b92..3a9bfc0 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c @@ -53,7 +53,7 @@ const char *RV32ISA = "RV32IMAC"; #define OPT_ENABLE_WRITABLE_FIOM 1001 #define OPT_PMP_COUNT 1002 #define OPT_PMP_GRAIN 1003 -#define OPT_ENABLE_SVINVAL 10017 +#define OPT_ENABLE_SVINVAL 1004 #define OPT_ENABLE_ZCB 10014 static bool do_dump_dts = false; |