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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-29 21:27:24 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-29 21:27:43 -0700 |
| commit | 7191d0cfb09fc0a31f729b6265190c7a444fbf51 (patch) | |
| tree | a1d3bc92ef833406986a2da79458257d5174f293 /c_emulator/riscv_sim.c | |
| parent | c50121c11c017b28914b9ba22b532c40fe09e6c3 (diff) | |
| download | sail-riscv-7191d0cfb09fc0a31f729b6265190c7a444fbf51.zip sail-riscv-7191d0cfb09fc0a31f729b6265190c7a444fbf51.tar.gz sail-riscv-7191d0cfb09fc0a31f729b6265190c7a444fbf51.tar.bz2 | |
Fix execution log.
Diffstat (limited to 'c_emulator/riscv_sim.c')
| -rw-r--r-- | c_emulator/riscv_sim.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c index da8b73c..864e2b7 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c @@ -186,11 +186,11 @@ char *process_args(int argc, char **argv) rv_enable_misaligned = true; break; case 'C': - fprintf(stderr, "enabling RVC compressed instructions.\n"); + fprintf(stderr, "disabling RVC compressed instructions.\n"); rv_enable_rvc = false; break; case 'I': - fprintf(stderr, "enabling writable misa CSR.\n"); + fprintf(stderr, "disabling writable misa CSR.\n"); rv_enable_writable_misa = false; break; case 'i': |