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| author | Bill McSpadden <bill@riscv.org> | 2023-02-13 19:50:46 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-02-13 19:50:46 -0600 |
| commit | 43b81eafc660ab584e1684668995957764a5e684 (patch) | |
| tree | 97aebab0afe29b8c0b1f8d9d4dc6a1c2c1f9afbe /c_emulator/riscv_platform_impl.c | |
| parent | 9547a30bf84572c458476591b569a95f5232c1c7 (diff) | |
| download | sail-riscv-43b81eafc660ab584e1684668995957764a5e684.zip sail-riscv-43b81eafc660ab584e1684668995957764a5e684.tar.gz sail-riscv-43b81eafc660ab584e1684668995957764a5e684.tar.bz2 | |
added 3 new command line switches (plus functionality): -X/--enable-experimental-extensions, --enable-smepmp, --enable-zicond (#219)
* added 3 command-line switches: -X/--enable-experimental-extensions, --enable-Smepmp, --enable-Zicond
* example commit
* fixed some type warnings/errors (between int/bool)
Diffstat (limited to 'c_emulator/riscv_platform_impl.c')
| -rw-r--r-- | c_emulator/riscv_platform_impl.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/c_emulator/riscv_platform_impl.c b/c_emulator/riscv_platform_impl.c index b1504a7..49b8cfd 100644 --- a/c_emulator/riscv_platform_impl.c +++ b/c_emulator/riscv_platform_impl.c @@ -14,6 +14,11 @@ bool rv_enable_dirty_update = false; bool rv_enable_misaligned = false; bool rv_mtval_has_illegal_inst_bits = false; +int rv_enable_Smepmp = 0; +int rv_enable_Zicond = 0; + +bool rv_enable_experimental_extensions = false; + uint64_t rv_ram_base = UINT64_C(0x80000000); uint64_t rv_ram_size = UINT64_C(0x4000000); |