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| author | Tim Hutt <timothy.hutt@codasip.com> | 2024-02-02 11:56:55 +0000 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2024-02-05 11:22:09 -0600 |
| commit | 4de2bff12d967d91dd064e4a49e25ca4785f25e3 (patch) | |
| tree | b106b03932811b9f35c4ac025a89c6f47862dc8f /c_emulator/riscv_platform.c | |
| parent | d5e89a71e3a84495c1b88a7749c25fd6b9da684b (diff) | |
| download | sail-riscv-4de2bff12d967d91dd064e4a49e25ca4785f25e3.zip sail-riscv-4de2bff12d967d91dd064e4a49e25ca4785f25e3.tar.gz sail-riscv-4de2bff12d967d91dd064e4a49e25ca4785f25e3.tar.bz2 | |
Improve PMP support
This implements a lot of missing functionality for PMPs.
* Support 64 PMPs as well as 0 and 16.
* Support setting PMP grain
* Return correct address bits on read (some read as 0 or 1 depending on the grain and match type)
* Unlock PMPs on reset
* Implement pmpcfg WARL legalisation
Co-authored-by: Ben Fletcher <benjamin.fletcher@codasip.com>
Diffstat (limited to 'c_emulator/riscv_platform.c')
| -rw-r--r-- | c_emulator/riscv_platform.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/c_emulator/riscv_platform.c b/c_emulator/riscv_platform.c index fbd63fa..253da35 100644 --- a/c_emulator/riscv_platform.c +++ b/c_emulator/riscv_platform.c @@ -47,6 +47,16 @@ bool sys_enable_vext(unit u) return rv_enable_vext; } +uint64_t sys_pmp_count(unit u) +{ + return rv_pmp_count; +} + +uint64_t sys_pmp_grain(unit u) +{ + return rv_pmp_grain; +} + bool sys_enable_writable_misa(unit u) { return rv_enable_writable_misa; @@ -67,11 +77,6 @@ bool plat_mtval_has_illegal_inst_bits(unit u) return rv_mtval_has_illegal_inst_bits; } -bool plat_enable_pmp(unit u) -{ - return rv_enable_pmp; -} - mach_bits plat_ram_base(unit u) { return rv_ram_base; |