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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-01-14 18:39:42 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-01-14 19:02:04 -0800 |
| commit | 3fdda1f2e054a01c95ff59593a8d67d85770609a (patch) | |
| tree | ce460b93f6240d98eaef659dbff2442402ee627d /c/riscv_platform_impl.h | |
| parent | 3c0168526eb9895292a6f92b42f243fce4fd1a9d (diff) | |
| download | sail-riscv-3fdda1f2e054a01c95ff59593a8d67d85770609a.zip sail-riscv-3fdda1f2e054a01c95ff59593a8d67d85770609a.tar.gz sail-riscv-3fdda1f2e054a01c95ff59593a8d67d85770609a.tar.bz2 | |
Reorganize directory structure.
Diffstat (limited to 'c/riscv_platform_impl.h')
| -rw-r--r-- | c/riscv_platform_impl.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/c/riscv_platform_impl.h b/c/riscv_platform_impl.h new file mode 100644 index 0000000..85e25c9 --- /dev/null +++ b/c/riscv_platform_impl.h @@ -0,0 +1,28 @@ +#pragma once + +#include <stdbool.h> +#include <stdint.h> + +/* Settings of the platform implementation. */ + +#define DEFAULT_RSTVEC 0x00001000 +#define SAIL_XLEN 64 + +extern bool rv_enable_dirty_update; +extern bool rv_enable_misaligned; +extern bool rv_mtval_has_illegal_inst_bits; + +extern uint64_t rv_ram_base; +extern uint64_t rv_ram_size; + +extern uint64_t rv_rom_base; +extern uint64_t rv_rom_size; + +extern uint64_t rv_clint_base; +extern uint64_t rv_clint_size; + +extern uint64_t rv_htif_tohost; +extern uint64_t rv_insns_per_tick; + +extern int term_fd; +void plat_term_write_impl(char c); |