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| author | James Clarke <jrtc27@jrtc27.com> | 2020-01-18 01:38:55 +0000 |
|---|---|---|
| committer | James Clarke <jrtc27@jrtc27.com> | 2020-01-18 01:38:55 +0000 |
| commit | fc8c86c8e104e445dcae9453aaf1cc0a2a42a551 (patch) | |
| tree | 04d8104aa00f2de71fbdec3acffbbb458b82f56a /Makefile | |
| parent | 3b771444de2ab918c8f5a7a2ddcab789dba8d977 (diff) | |
| download | sail-riscv-fc8c86c8e104e445dcae9453aaf1cc0a2a42a551.zip sail-riscv-fc8c86c8e104e445dcae9453aaf1cc0a2a42a551.tar.gz sail-riscv-fc8c86c8e104e445dcae9453aaf1cc0a2a42a551.tar.bz2 | |
Allow extensions to provide their own exception codes/names
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -51,10 +51,10 @@ SAIL_REGS_SRCS += riscv_pmp_regs.sail riscv_pmp_control.sail SAIL_REGS_SRCS += riscv_ext_regs.sail $(SAIL_CHECK_SRCS) SAIL_ARCH_SRCS = $(PRELUDE) -SAIL_ARCH_SRCS += riscv_types_ext.sail riscv_types.sail +SAIL_ARCH_SRCS += riscv_types_common.sail riscv_types_ext.sail riscv_types.sail SAIL_ARCH_SRCS += riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS) -SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) +SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_decode_ext.sail riscv_fetch.sail riscv_step.sail RVFI_STEP_SRCS = riscv_step_common.sail riscv_step_rvfi.sail riscv_decode_ext.sail riscv_fetch_rvfi.sail riscv_step.sail |