diff options
| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-07-22 18:07:58 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-07-22 18:14:10 -0700 |
| commit | fb341ef48e8c6518616394da64881ec0d79fd51c (patch) | |
| tree | 6e3bcae979ed14db6251e1a2ef5caff4a16f61f4 /Makefile | |
| parent | bf32b39f88d88a9b5d1002b714190db5bdd2b8ec (diff) | |
| download | sail-riscv-fb341ef48e8c6518616394da64881ec0d79fd51c.zip sail-riscv-fb341ef48e8c6518616394da64881ec0d79fd51c.tar.gz sail-riscv-fb341ef48e8c6518616394da64881ec0d79fd51c.tar.bz2 | |
Make a custom exception code available for extensions, and remove the E_CHERI code. Enable extensions for PTE checks and PTW errors, and propagate those into exception codes.
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 4 |
1 files changed, 3 insertions, 1 deletions
@@ -50,7 +50,9 @@ SAIL_REGS_SRCS = riscv_reg_type.sail riscv_regs.sail riscv_pc_access.sail riscv_ SAIL_REGS_SRCS += riscv_pmp_regs.sail riscv_pmp_control.sail SAIL_REGS_SRCS += riscv_ext_regs.sail $(SAIL_CHECK_SRCS) -SAIL_ARCH_SRCS = $(PRELUDE) riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail +SAIL_ARCH_SRCS = $(PRELUDE) +SAIL_ARCH_SRCS += riscv_types_ext.sail riscv_types.sail +SAIL_ARCH_SRCS += riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS) SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_decode_ext.sail riscv_fetch.sail riscv_step.sail |