diff options
| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-01-22 09:10:54 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-01-22 09:10:54 -0800 |
| commit | fadd57c7514709f94b90073640e7e9e600c46539 (patch) | |
| tree | cd96acccb414d576ac5dd84b2efaff2eb57703a3 /Makefile | |
| parent | 7ecffb236dfe31200b50d5e4064a4d42caebbab2 (diff) | |
| parent | 2c4ef9f0c252cddcae7df516750110db285dd87d (diff) | |
| download | sail-riscv-fadd57c7514709f94b90073640e7e9e600c46539.zip sail-riscv-fadd57c7514709f94b90073640e7e9e600c46539.tar.gz sail-riscv-fadd57c7514709f94b90073640e7e9e600c46539.tar.bz2 | |
Merge branch 'master' into rsnikhil
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -60,10 +60,10 @@ SAIL_REGS_SRCS += riscv_pmp_regs.sail riscv_pmp_control.sail SAIL_REGS_SRCS += riscv_ext_regs.sail $(SAIL_CHECK_SRCS) SAIL_ARCH_SRCS = $(PRELUDE) -SAIL_ARCH_SRCS += riscv_types_ext.sail riscv_types.sail +SAIL_ARCH_SRCS += riscv_types_common.sail riscv_types_ext.sail riscv_types.sail SAIL_ARCH_SRCS += riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS) -SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) +SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_decode_ext.sail riscv_fetch.sail riscv_step.sail RVFI_STEP_SRCS = riscv_step_common.sail riscv_step_rvfi.sail riscv_decode_ext.sail riscv_fetch_rvfi.sail riscv_step.sail |