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| author | Robert Norton <rmn30@cam.ac.uk> | 2019-04-29 14:31:18 +0100 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-04-29 16:22:38 -0700 |
| commit | f14e8ebac39bf6771f0d1775d5145f7f6549c5ea (patch) | |
| tree | f6ec2ea0e26c1716dd10e9d19ae8d55ae2f8d06e /Makefile | |
| parent | eb176111887b6dc1a52d17bcac1a4bdd8af4d4fc (diff) | |
| download | sail-riscv-f14e8ebac39bf6771f0d1775d5145f7f6549c5ea.zip sail-riscv-f14e8ebac39bf6771f0d1775d5145f7f6549c5ea.tar.gz sail-riscv-f14e8ebac39bf6771f0d1775d5145f7f6549c5ea.tar.bz2 | |
Add a post decode hook aimed at implementing CHERI capability mode.
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -47,8 +47,8 @@ SAIL_REGS_SRCS = riscv_reg_type.sail riscv_regs.sail riscv_sys_regs.sail riscv_e SAIL_ARCH_SRCS = $(PRELUDE) riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS) SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) -SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_fetch.sail riscv_step.sail -RVFI_STEP_SRCS = riscv_step_common.sail riscv_step_rvfi.sail riscv_fetch_rvfi.sail riscv_step.sail +SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_decode_ext.sail riscv_fetch.sail riscv_step.sail +RVFI_STEP_SRCS = riscv_step_common.sail riscv_step_rvfi.sail riscv_decode_ext.sail riscv_fetch_rvfi.sail riscv_step.sail # Control inclusion of 64-bit only riscv_analysis ifeq ($(ARCH),RV32) |