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| author | Jon French <jf451@cam.ac.uk> | 2018-05-10 11:32:15 +0100 |
|---|---|---|
| committer | Jon French <jf451@cam.ac.uk> | 2018-05-10 11:32:51 +0100 |
| commit | ae49c2b7d8bb7ec577b9a4d1d7fdd7a5f010df49 (patch) | |
| tree | ca52deea44c6b2c94defe5ed5703d0973414f421 /Makefile | |
| parent | 9c63faa591c02413eace7ed1182d6c6a3f663f8d (diff) | |
| download | sail-riscv-ae49c2b7d8bb7ec577b9a4d1d7fdd7a5f010df49.zip sail-riscv-ae49c2b7d8bb7ec577b9a4d1d7fdd7a5f010df49.tar.gz sail-riscv-ae49c2b7d8bb7ec577b9a4d1d7fdd7a5f010df49.tar.bz2 | |
riscv/Makefile: add SAIL variable for easier debugging
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 11 |
1 files changed, 6 insertions, 5 deletions
@@ -1,21 +1,22 @@ SAIL_SRCS = prelude.sail riscv_types.sail riscv_mem.sail riscv_sys.sail riscv_vmem.sail riscv.sail SAIL_DIR ?= $(realpath ..) +SAIL ?= $(SAIL_DIR)/sail export SAIL_DIR all: riscv Riscv.thy check: $(SAIL_SRCS) main.sail Makefile - $(SAIL_DIR)/sail $(SAIL_FLAGS) $(SAIL_SRCS) main.sail + $(SAIL) $(SAIL_FLAGS) $(SAIL_SRCS) main.sail riscv: $(SAIL_SRCS) main.sail Makefile - $(SAIL_DIR)/sail $(SAIL_FLAGS) -ocaml -o riscv $(SAIL_SRCS) main.sail + $(SAIL) $(SAIL_FLAGS) -ocaml -o riscv $(SAIL_SRCS) main.sail riscv_duopod_ocaml: prelude.sail riscv_duopod.sail - $(SAIL_DIR)/sail $(SAIL_FLAGS) -ocaml -o $@ $^ + $(SAIL) $(SAIL_FLAGS) -ocaml -o $@ $^ riscv_duopod.lem: prelude.sail riscv_duopod.sail - $(SAIL_DIR)/sail $(SAIL_FLAGS) -lem -lem_mwords -lem_lib Riscv_extras -o riscv_duopod $^ + $(SAIL) $(SAIL_FLAGS) -lem -lem_mwords -lem_lib Riscv_extras -o riscv_duopod $^ Riscv_duopod.thy: riscv_duopod.lem riscv_extras.lem lem -isa -outdir . -lib ../src/lem_interp -lib ../src/gen_lib \ riscv_extras.lem \ @@ -32,7 +33,7 @@ Riscv.thy: riscv.lem riscv_extras.lem sed -i 's/datatype ast/datatype (plugins only: size) ast/' Riscv_types.thy riscv.lem: $(SAIL_SRCS) Makefile - $(SAIL_DIR)/sail $(SAIL_FLAGS) -lem -o riscv -lem_mwords -lem_lib Riscv_extras $(SAIL_SRCS) + $(SAIL) $(SAIL_FLAGS) -lem -o riscv -lem_mwords -lem_lib Riscv_extras $(SAIL_SRCS) clean: -rm -rf riscv _sbuild |