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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-17 19:09:27 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-17 19:09:27 -0700 |
| commit | 918afe11c45fe207bd15ca0d9d79afe8a20de4c7 (patch) | |
| tree | aa649fce289cba8eb94281130ca838cab7c0bed5 /Makefile | |
| parent | 5dc38f37b871af7d6d1af9dfbbb203fb92d99d6a (diff) | |
| download | sail-riscv-918afe11c45fe207bd15ca0d9d79afe8a20de4c7.zip sail-riscv-918afe11c45fe207bd15ca0d9d79afe8a20de4c7.tar.gz sail-riscv-918afe11c45fe207bd15ca0d9d79afe8a20de4c7.tar.bz2 | |
Add basic PMP definitions.
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -45,7 +45,7 @@ endif # Non-instruction sources PRELUDE = prelude.sail prelude_mapping.sail $(SAIL_XLEN) prelude_mem_metadata.sail prelude_mem.sail -SAIL_REGS_SRCS = riscv_reg_type.sail riscv_regs.sail riscv_pc_access.sail riscv_sys_regs.sail riscv_ext_regs.sail $(SAIL_CHECK_SRCS) +SAIL_REGS_SRCS = riscv_reg_type.sail riscv_regs.sail riscv_pc_access.sail riscv_sys_regs.sail riscv_pmp_regs.sail riscv_ext_regs.sail $(SAIL_CHECK_SRCS) SAIL_ARCH_SRCS = $(PRELUDE) riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS) SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) |