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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-20 14:26:27 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-20 17:10:50 -0700 |
| commit | 20c226fe0b35dab223cf6fac82c3c9962365af3d (patch) | |
| tree | 5c197f09c7052632ce3c78a8d1da98a5130daf7b /Makefile | |
| parent | 42531fe799eb4025f35e57cffe0ab60c99014b63 (diff) | |
| download | sail-riscv-20c226fe0b35dab223cf6fac82c3c9962365af3d.zip sail-riscv-20c226fe0b35dab223cf6fac82c3c9962365af3d.tar.gz sail-riscv-20c226fe0b35dab223cf6fac82c3c9962365af3d.tar.bz2 | |
Add PMP address and entry matching, and priority logic.
This is specialized for now for the smallest PMP grain of 4 bytes.
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 6 |
1 files changed, 5 insertions, 1 deletions
@@ -45,7 +45,11 @@ endif # Non-instruction sources PRELUDE = prelude.sail prelude_mapping.sail $(SAIL_XLEN) prelude_mem_metadata.sail prelude_mem.sail -SAIL_REGS_SRCS = riscv_reg_type.sail riscv_regs.sail riscv_pc_access.sail riscv_sys_regs.sail riscv_pmp_regs.sail riscv_ext_regs.sail $(SAIL_CHECK_SRCS) + +SAIL_REGS_SRCS = riscv_reg_type.sail riscv_regs.sail riscv_pc_access.sail riscv_sys_regs.sail +SAIL_REGS_SRCS += riscv_pmp_regs.sail riscv_pmp_control.sail +SAIL_REGS_SRCS += riscv_ext_regs.sail $(SAIL_CHECK_SRCS) + SAIL_ARCH_SRCS = $(PRELUDE) riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS) SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) |