aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-02-06 12:04:28 -0800
committerPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-02-06 12:04:28 -0800
commitf94b8e438f25400b9ad188f05386fd54c6e76b41 (patch)
tree0eb0b4bf4306b0ae04ec131c34e8037ecdf5c202
parent19eb59841c3dd3eee570e66496e9333973d7d9bf (diff)
downloadsail-riscv-f94b8e438f25400b9ad188f05386fd54c6e76b41.zip
sail-riscv-f94b8e438f25400b9ad188f05386fd54c6e76b41.tar.gz
sail-riscv-f94b8e438f25400b9ad188f05386fd54c6e76b41.tar.bz2
Fix register rs2 read in AMO.
-rw-r--r--model/riscv_insts_aext.sail2
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_insts_aext.sail b/model/riscv_insts_aext.sail
index 3b74ac6..2f93cc5 100644
--- a/model/riscv_insts_aext.sail
+++ b/model/riscv_insts_aext.sail
@@ -180,6 +180,7 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = {
DOUBLE => mem_write_ea(addr, 8, aq & rl, rl, true),
_ => internal_error ("AMO expected WORD or DOUBLE")
};
+ rs2_val : xlenbits = X(rs2);
match (eares) {
MemException(e) => { handle_mem_exception(addr, e); false },
MemValue(_) => {
@@ -191,7 +192,6 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = {
match (rval) {
MemException(e) => { handle_mem_exception(addr, e); false },
MemValue(loaded) => {
- rs2_val : xlenbits = X(rs2);
result : xlenbits =
match op {
AMOSWAP => rs2_val,