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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-04-26 10:25:30 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-04-26 10:25:30 -0700 |
| commit | ecc71c20a45c96bb206cb6185c8b25319ddaaecb (patch) | |
| tree | 917f59e387f95a26b05288e1bc9b1248406f67bd | |
| parent | f5a5aa54c3f676c3cb3f8fc50fc4ab2754832d38 (diff) | |
| download | sail-riscv-ecc71c20a45c96bb206cb6185c8b25319ddaaecb.zip sail-riscv-ecc71c20a45c96bb206cb6185c8b25319ddaaecb.tar.gz sail-riscv-ecc71c20a45c96bb206cb6185c8b25319ddaaecb.tar.bz2 | |
Fix bug introduced in alignment check.
| -rw-r--r-- | riscv_mem.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv_mem.sail b/riscv_mem.sail index 67c35bc..375f48b 100644 --- a/riscv_mem.sail +++ b/riscv_mem.sail @@ -6,7 +6,7 @@ union MemoryOpResult ('a : Type) = { } function is_aligned_addr (addr : xlenbits, width : atom('n)) -> forall 'n. bool = - unsigned(addr) % width != 0 + unsigned(addr) % width == 0 function checked_mem_read(t : ReadType, addr : xlenbits, width : atom('n)) -> forall 'n. MemoryOpResult(bits(8 * 'n)) = match (t, __RISCV_read(addr, width)) { |