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| author | ahadali5000 <ahad.ali@10xengineers.ai> | 2023-09-26 10:42:45 +0500 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2023-09-26 05:56:08 -0500 |
| commit | dbea780cf463d8fec7601064e9515d4384cbbebb (patch) | |
| tree | 59b0e7b7fa70530915cf515e425afa41af04fa79 | |
| parent | 24e3e68acae898b3c2106481005e16a9568b458a (diff) | |
| download | sail-riscv-dbea780cf463d8fec7601064e9515d4384cbbebb.zip sail-riscv-dbea780cf463d8fec7601064e9515d4384cbbebb.tar.gz sail-riscv-dbea780cf463d8fec7601064e9515d4384cbbebb.tar.bz2 | |
Per section 3.1.1 of the Privileged Spec (Machine ISA Register misa): F/D both should be disabled if F=0
| -rw-r--r-- | model/riscv_sys_regs.sail | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index 4774469..cb44664 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -164,10 +164,10 @@ function legalize_misa(m : Misa, v : xlenbits) -> Misa = { else { /* Suppress enabling C if C was disabled at boot (i.e. not supported) */ let m = if not(sys_enable_rvc()) then m else update_C(m, v.C()); - /* Handle updates for F/D. */ - if not(sys_enable_fdext()) | (v.D() == 0b1 & v.F() == 0b0) + /* Suppress updates to misa.{f,d} if disabled at boot */ + if not(sys_enable_fdext()) then m - else update_D(update_F(m, v.F()), v.D()) + else update_D(update_F(m, v.F()), v.D() & v.F()) } } |