diff options
| author | Tim Hutt <timothy.hutt@codasip.com> | 2024-06-12 11:21:47 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-06-12 11:21:47 +0100 |
| commit | ba35af52e8ee57b7b30772490e9e35d537c769d9 (patch) | |
| tree | d24fa569d5ba062b7fa76825d0557f7976be1442 | |
| parent | 7ff6d94ebf2335761245e714714b7fcd7919b0fb (diff) | |
| download | sail-riscv-ba35af52e8ee57b7b30772490e9e35d537c769d9.zip sail-riscv-ba35af52e8ee57b7b30772490e9e35d537c769d9.tar.gz sail-riscv-ba35af52e8ee57b7b30772490e9e35d537c769d9.tar.bz2 | |
Check misalignment of AMOs before address translation (#471)
This is optional according to the spec - you can check afterwards. However
1. it seems extremely unlikely that any real designs will do that for atomics, which (ignoring Zam which the model doesn't support yet), always have to be aligned, and
2. the LR and SC instructions already check before address translation, so this wasn't even consistent.
Ideally in future this would be configurable.
| -rw-r--r-- | model/riscv_insts_aext.sail | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/model/riscv_insts_aext.sail b/model/riscv_insts_aext.sail index 7a7e492..00bf0d1 100644 --- a/model/riscv_insts_aext.sail +++ b/model/riscv_insts_aext.sail @@ -180,7 +180,9 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = { match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width_bytes) { Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { + if not(is_aligned(vaddr, width)) + then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, ReadWrite(Data, Data)) { TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, TR_Address(addr, _) => { let eares = mem_write_ea(addr, width_bytes, aq & rl, rl, true); |