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author | Jordan Carlin <jordanmcarlin@gmail.com> | 2024-05-18 00:12:55 -0700 |
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committer | Alasdair Armstrong <alasdair.armstrong@googlemail.com> | 2024-05-19 00:24:46 +0100 |
commit | aad365d4629412a2b74dec5436fb67d1f9df804b (patch) | |
tree | bbd1161e89a0fad7b0a09439f543a76b363b99b8 | |
parent | 2259041cd6ef4d4e5acc6c8232e623e79476f408 (diff) | |
download | sail-riscv-aad365d4629412a2b74dec5436fb67d1f9df804b.zip sail-riscv-aad365d4629412a2b74dec5436fb67d1f9df804b.tar.gz sail-riscv-aad365d4629412a2b74dec5436fb67d1f9df804b.tar.bz2 |
Remove effect from vext_vset
-rw-r--r-- | model/riscv_insts_vext_vset.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_insts_vext_vset.sail b/model/riscv_insts_vext_vset.sail index 000b2f3..40a7ea9 100644 --- a/model/riscv_insts_vext_vset.sail +++ b/model/riscv_insts_vext_vset.sail @@ -41,7 +41,7 @@ mapping maybe_ma_flag : string <-> bits(1) = { sep() ^ "mu" <-> 0b0 } -val handle_illegal_vtype : unit -> unit effect {rreg} +val handle_illegal_vtype : unit -> unit function handle_illegal_vtype() = { /* Note: Implementations can set vill or trap if the vtype setting is not supported. * TODO: configuration support for both solutions |