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| author | Alasdair <alasdair.armstrong@cl.cam.ac.uk> | 2024-03-01 19:57:18 +0000 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2024-04-24 08:38:22 -0500 |
| commit | a39a1ac64e8e716c5bb588f11809dec661ae0f1d (patch) | |
| tree | 55eec6165217f110d1dcf3b403f2e935f70cfda0 | |
| parent | 16077e126b634c006590b02cb758d48a3882528a (diff) | |
| download | sail-riscv-a39a1ac64e8e716c5bb588f11809dec661ae0f1d.zip sail-riscv-a39a1ac64e8e716c5bb588f11809dec661ae0f1d.tar.gz sail-riscv-a39a1ac64e8e716c5bb588f11809dec661ae0f1d.tar.bz2 | |
Add read-only CSR MCONFIGPTR
CSR MCONFIGPTR is defined in RISCV priv spec 1.12 but is missing from the
RISC-V SAIL model. This commit adds the read-only CSR MCONFIGPTR.
Co-authored-by: Dan Smathers <dan.smathers@seagate.com>
| -rw-r--r-- | model/riscv_csr_map.sail | 1 | ||||
| -rw-r--r-- | model/riscv_insts_zicsr.sail | 1 | ||||
| -rw-r--r-- | model/riscv_sys_control.sail | 2 | ||||
| -rw-r--r-- | model/riscv_sys_regs.sail | 1 |
4 files changed, 5 insertions, 0 deletions
diff --git a/model/riscv_csr_map.sail b/model/riscv_csr_map.sail index 9e3e804..22cffd5 100644 --- a/model/riscv_csr_map.sail +++ b/model/riscv_csr_map.sail @@ -58,6 +58,7 @@ mapping clause csr_name_map = 0xF11 <-> "mvendorid" mapping clause csr_name_map = 0xF12 <-> "marchid" mapping clause csr_name_map = 0xF13 <-> "mimpid" mapping clause csr_name_map = 0xF14 <-> "mhartid" +mapping clause csr_name_map = 0xF15 <-> "mconfigptr" /* machine trap setup */ mapping clause csr_name_map = 0x300 <-> "mstatus" mapping clause csr_name_map = 0x301 <-> "misa" diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail index d106ad2..7c52abd 100644 --- a/model/riscv_insts_zicsr.sail +++ b/model/riscv_insts_zicsr.sail @@ -29,6 +29,7 @@ function readCSR csr : csreg -> xlenbits = { (0xF12, _) => marchid, (0xF13, _) => mimpid, (0xF14, _) => mhartid, + (0xF15, _) => mconfigptr, (0x300, _) => mstatus.bits, (0x301, _) => misa.bits, (0x302, _) => medeleg.bits, diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index ecc53ae..1baa337 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -21,6 +21,7 @@ function is_CSR_defined (csr : csreg, p : Privilege) -> bool = 0xf12 => p == Machine, // marchdid 0xf13 => p == Machine, // mimpid 0xf14 => p == Machine, // mhartid + 0xf15 => p == Machine, // mconfigptr /* machine mode: trap setup */ 0x300 => p == Machine, // mstatus 0x301 => p == Machine, // misa @@ -477,6 +478,7 @@ function init_sys() -> unit = { cur_privilege = Machine; mhartid = zero_extend(0b0); + mconfigptr = zero_extend(0b0); misa[MXL] = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64); misa[A] = 0b1; /* atomics */ diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index 3e198b4..f3cd7e3 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -515,6 +515,7 @@ register mimpid : xlenbits register marchid : xlenbits /* TODO: this should be readonly, and always 0 for now */ register mhartid : xlenbits +register mconfigptr : xlenbits /* S-mode registers */ |