diff options
| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-01-25 12:38:24 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-01-25 12:38:24 -0800 |
| commit | 89cf6f8525ba5ecb67d29302b7cf3233e7553ba4 (patch) | |
| tree | 0ebe8b392f19493f50c048ff763d51a1a0c3bace | |
| parent | 9fa19dea706381e2a9c0c4aa226124adaf328f1a (diff) | |
| download | sail-riscv-89cf6f8525ba5ecb67d29302b7cf3233e7553ba4.zip sail-riscv-89cf6f8525ba5ecb67d29302b7cf3233e7553ba4.tar.gz sail-riscv-89cf6f8525ba5ecb67d29302b7cf3233e7553ba4.tar.bz2 | |
SRET should be illegal if S-mode is not supported.
| -rw-r--r-- | model/riscv_insts_base.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail index 7013fbf..396b49c 100644 --- a/model/riscv_insts_base.sail +++ b/model/riscv_insts_base.sail @@ -600,7 +600,7 @@ mapping clause encdec = SRET() function clause execute SRET() = { match cur_privilege { User => handle_illegal(), - Supervisor => if mstatus.TSR() == true + Supervisor => if (~ (haveSupMode ())) | mstatus.TSR() == true then handle_illegal() else nextPC = handle_exception(cur_privilege, CTL_SRET(), PC), Machine => nextPC = handle_exception(cur_privilege, CTL_SRET(), PC) |