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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-07 16:51:24 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-07 16:51:24 -0700 |
| commit | 6f2c930fcf25fad5a40d1107c4ae289a55af4631 (patch) | |
| tree | 1659da886b8fbf3a5ea2228f94f7d24d28fae136 | |
| parent | 0856a511e198b063c555f69bac7586a7dc39879f (diff) | |
| download | sail-riscv-6f2c930fcf25fad5a40d1107c4ae289a55af4631.zip sail-riscv-6f2c930fcf25fad5a40d1107c4ae289a55af4631.tar.gz sail-riscv-6f2c930fcf25fad5a40d1107c4ae289a55af4631.tar.bz2 | |
Allow overrides for mtvec/stvec accessors.
| -rw-r--r-- | model/riscv_insts_zicsr.sail | 8 | ||||
| -rw-r--r-- | model/riscv_sys_exceptions.sail | 18 |
2 files changed, 22 insertions, 4 deletions
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail index ae88680..569bc19 100644 --- a/model/riscv_insts_zicsr.sail +++ b/model/riscv_insts_zicsr.sail @@ -26,7 +26,7 @@ function readCSR csr : csreg -> xlenbits = { (0x302, _) => medeleg.bits(), (0x303, _) => mideleg.bits(), (0x304, _) => mie.bits(), - (0x305, _) => mtvec.bits(), + (0x305, _) => get_mtvec(), (0x306, _) => EXTZ(mcounteren.bits()), (0x340, _) => mscratch, (0x341, _) => get_xret_target(Machine) & pc_alignment_mask(), @@ -51,7 +51,7 @@ function readCSR csr : csreg -> xlenbits = { (0x102, _) => sedeleg.bits(), (0x103, _) => sideleg.bits(), (0x104, _) => lower_mie(mie, mideleg).bits(), - (0x105, _) => stvec.bits(), + (0x105, _) => get_stvec(), (0x106, _) => EXTZ(scounteren.bits()), (0x140, _) => sscratch, (0x141, _) => get_xret_target(Supervisor) & pc_alignment_mask(), @@ -88,7 +88,7 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = { (0x302, _) => { medeleg = legalize_medeleg(medeleg, value); Some(medeleg.bits()) }, (0x303, _) => { mideleg = legalize_mideleg(mideleg, value); Some(mideleg.bits()) }, (0x304, _) => { mie = legalize_mie(mie, value); Some(mie.bits()) }, - (0x305, _) => { mtvec = legalize_tvec(mtvec, value); Some(mtvec.bits()) }, + (0x305, _) => { Some(set_mtvec(value)) }, (0x306, _) => { mcounteren = legalize_mcounteren(mcounteren, value); Some(EXTZ(mcounteren.bits())) }, (0x340, _) => { mscratch = value; Some(mscratch) }, (0x341, _) => { Some(set_xret_target(Machine, value)) }, @@ -113,7 +113,7 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = { (0x102, _) => { sedeleg = legalize_sedeleg(sedeleg, value); Some(sedeleg.bits()) }, (0x103, _) => { sideleg->bits() = value; Some(sideleg.bits()) }, /* TODO: does this need legalization? */ (0x104, _) => { mie = legalize_sie(mie, mideleg, value); Some(mie.bits()) }, - (0x105, _) => { stvec = legalize_tvec(stvec, value); Some(stvec.bits()) }, + (0x105, _) => { Some(set_stvec(value)) }, (0x106, _) => { scounteren = legalize_scounteren(scounteren, value); Some(EXTZ(scounteren.bits())) }, (0x140, _) => { sscratch = value; Some(sscratch) }, (0x141, _) => { Some(set_xret_target(Supervisor, value)) }, diff --git a/model/riscv_sys_exceptions.sail b/model/riscv_sys_exceptions.sail index ce28939..d63b0a9 100644 --- a/model/riscv_sys_exceptions.sail +++ b/model/riscv_sys_exceptions.sail @@ -36,3 +36,21 @@ function set_xret_target(p, value) = { }; target } + +/* other trap-related CSRs */ + +function get_mtvec() -> xlenbits = + mtvec.bits() + +function get_stvec() -> xlenbits = + stvec.bits() + +function set_mtvec(value : xlenbits) -> xlenbits = { + mtvec = legalize_tvec(mtvec, value); + mtvec.bits() +} + +function set_stvec(value : xlenbits) -> xlenbits = { + stvec = legalize_tvec(stvec, value); + stvec.bits() +} |