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| author | Tim Hutt <timothy.hutt@codasip.com> | 2023-08-16 15:10:08 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-09-12 13:50:59 +0200 |
| commit | 6c7cb9bdbac76cb61512b48be0cb3aeb5c42e80d (patch) | |
| tree | 1c8e6a3c39726d7528c234fcc30679024a544de7 | |
| parent | e0d42a8562d247511c776fcb889176b2ce3a6cf2 (diff) | |
| download | sail-riscv-6c7cb9bdbac76cb61512b48be0cb3aeb5c42e80d.zip sail-riscv-6c7cb9bdbac76cb61512b48be0cb3aeb5c42e80d.tar.gz sail-riscv-6c7cb9bdbac76cb61512b48be0cb3aeb5c42e80d.tar.bz2 | |
Fix some stray tabs
| -rw-r--r-- | model/riscv_vmem_sv39.sail | 4 | ||||
| -rw-r--r-- | model/riscv_vmem_sv48.sail | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/model/riscv_vmem_sv39.sail b/model/riscv_vmem_sv39.sail index 12f1eaf..5bc5a18 100644 --- a/model/riscv_vmem_sv39.sail +++ b/model/riscv_vmem_sv39.sail @@ -111,7 +111,7 @@ function walk39(vaddr, ac, priv, mxr, do_sum, ptb, level, global, ext_ptw) = { } } else { /* leaf PTE */ match checkPTEPermission(ac, priv, mxr, do_sum, pattr, ext_pte, ext_ptw) { - PTE_Check_Failure(ext_ptw, ext_ptw_fail) => { + PTE_Check_Failure(ext_ptw, ext_ptw_fail) => { /* print("walk39: pte permission check failure"); */ PTW_Failure(ext_get_ptw_error(ext_ptw_fail), ext_ptw) }, @@ -232,7 +232,7 @@ function translate39(asid, ptb, vAddr, ac, priv, mxr, do_sum, level, ext_ptw) = TR_Failure(PTW_PTE_Update(), ext_ptw) } else { w_pte : SV39_PTE = update_BITS(pte, pbits.bits()); - w_pte : SV39_PTE = update_Ext(w_pte, ext); + w_pte : SV39_PTE = update_Ext(w_pte, ext); match mem_write_value_priv(zero_extend(pteAddr), 8, w_pte.bits(), Supervisor, false, false, false) { MemValue(_) => { add_to_TLB39(asid, vAddr, pAddr, w_pte, pteAddr, level, global); diff --git a/model/riscv_vmem_sv48.sail b/model/riscv_vmem_sv48.sail index 601ed0f..26a8a3b 100644 --- a/model/riscv_vmem_sv48.sail +++ b/model/riscv_vmem_sv48.sail @@ -115,7 +115,7 @@ function walk48(vaddr, ac, priv, mxr, do_sum, ptb, level, global, ext_ptw) = { /* print("walk48: pte permission check failure"); */ PTW_Failure(ext_get_ptw_error(ext_ptw_fail), ext_ptw) }, - PTE_Check_Success(ext_ptw) => { + PTE_Check_Success(ext_ptw) => { if level > 0 then { /* superpage */ /* fixme hack: to get a mask of appropriate size */ let mask = shiftl(pte.PPNi() ^ pte.PPNi() ^ zero_extend(0b1), level * SV48_LEVEL_BITS) - 1; @@ -196,7 +196,7 @@ function translate48(asid, ptb, vAddr, ac, priv, mxr, do_sum, level, ext_ptw) = TR_Failure(PTW_PTE_Update(), ext_ptw) } else { w_pte : SV48_PTE = update_BITS(pte, pbits.bits()); - w_pte : SV48_PTE = update_Ext(w_pte, ext); + w_pte : SV48_PTE = update_Ext(w_pte, ext); match mem_write_value_priv(zero_extend(pteAddr), 8, w_pte.bits(), Supervisor, false, false, false) { MemValue(_) => { add_to_TLB48(asid, vAddr, pAddr, w_pte, pteAddr, level, global); |