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| author | Robert Norton <rmn30@cam.ac.uk> | 2019-06-27 15:12:41 +0100 |
|---|---|---|
| committer | Robert Norton <rmn30@cam.ac.uk> | 2019-06-27 15:12:41 +0100 |
| commit | 21a1d180b49da0ae934eaa0aaeb2f3b617cf014d (patch) | |
| tree | 99aaaf273183a9d7bd166ea61cfd305bd481e096 | |
| parent | 57694dc5a53d84a0d9299b59c45676eacf121bc7 (diff) | |
| download | sail-riscv-21a1d180b49da0ae934eaa0aaeb2f3b617cf014d.zip sail-riscv-21a1d180b49da0ae934eaa0aaeb2f3b617cf014d.tar.gz sail-riscv-21a1d180b49da0ae934eaa0aaeb2f3b617cf014d.tar.bz2 | |
Predicate more tracing with get_config_print_xxx.
| -rw-r--r-- | model/riscv_mem.sail | 9 | ||||
| -rw-r--r-- | model/riscv_regs.sail | 3 | ||||
| -rw-r--r-- | model/riscv_step.sail | 3 |
3 files changed, 10 insertions, 5 deletions
diff --git a/model/riscv_mem.sail b/model/riscv_mem.sail index 6b9d46c..00c5561 100644 --- a/model/riscv_mem.sail +++ b/model/riscv_mem.sail @@ -22,8 +22,10 @@ function phys_mem_read forall 'n, 'n > 0. (t : ReadType, addr : xlenbits, width match (t, result) { (Instruction, None()) => MemException(E_Fetch_Access_Fault), (Data, None()) => MemException(E_Load_Access_Fault), - (_, Some(v)) => { print_mem("mem[" ^ t ^ "," ^ BitStr(addr) ^ "] -> " ^ BitStr(v)); - MemValue(v) } + (_, Some(v)) => { if get_config_print_mem() then + print_mem("mem[" ^ t ^ "," ^ BitStr(addr) ^ "] -> " ^ BitStr(v)); + MemValue(v) + } } } @@ -118,7 +120,8 @@ function phys_mem_write forall 'n, 'n > 0. (addr : xlenbits, width : atom('n), d (true, false, true) => throw(Error_not_implemented("sc.aq")), (true, true , true) => MemValue(write_ram(Write_RISCV_conditional_strong_release, addr, width, data, meta)) }) : MemoryOpResult(bool); - print_mem("mem[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data)); + if get_config_print_mem() then + print_mem("mem[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data)); result } diff --git a/model/riscv_regs.sail b/model/riscv_regs.sail index b92f234..eacc645 100644 --- a/model/riscv_regs.sail +++ b/model/riscv_regs.sail @@ -134,7 +134,8 @@ function wX (r, in_v) = { }; if (r != 0) then { rvfi_wX(r, in_v); - print_reg("x" ^ string_of_int(r) ^ " <- " ^ RegStr(v)); + if get_config_print_reg() then + print_reg("x" ^ string_of_int(r) ^ " <- " ^ RegStr(v)); } } diff --git a/model/riscv_step.sail b/model/riscv_step.sail index 12c8522..7151b69 100644 --- a/model/riscv_step.sail +++ b/model/riscv_step.sail @@ -10,7 +10,8 @@ function step(step_no) = { let (retired, stepped) : (Retired, bool) = match dispatchInterrupt(cur_privilege) { Some(intr, priv) => { - print_bits("Handling interrupt: ", intr); + if get_config_print_instr() then + print_bits("Handling interrupt: ", intr); handle_interrupt(intr, priv); (RETIRE_FAIL, false) }, |