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authorMartin Berger <contact@martinfriedrichberger.net>2024-04-30 00:17:45 +0100
committerBill McSpadden <bill@riscv.org>2024-05-07 19:56:04 -0500
commit0f2f54cb43c1fe84da1d1cd2f96ea6a0500c93d4 (patch)
tree372360c61c6d1dc6af30d69e00c2a33bf86cc7f0
parent66095cacc025de50eddeccb5d0f166846df1a717 (diff)
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fixup! fixup! Add Svinval extension.
-rw-r--r--c_emulator/riscv_platform.c1
-rw-r--r--ocaml_emulator/platform.ml4
2 files changed, 2 insertions, 3 deletions
diff --git a/c_emulator/riscv_platform.c b/c_emulator/riscv_platform.c
index 2bd5c63..5b98528 100644
--- a/c_emulator/riscv_platform.c
+++ b/c_emulator/riscv_platform.c
@@ -37,7 +37,6 @@ bool sys_enable_svinval(unit u)
return rv_enable_svinval;
}
-
bool sys_enable_zcb(unit u)
{
return rv_enable_zcb;
diff --git a/ocaml_emulator/platform.ml b/ocaml_emulator/platform.ml
index 1d2f3de..69f2714 100644
--- a/ocaml_emulator/platform.ml
+++ b/ocaml_emulator/platform.ml
@@ -10,7 +10,7 @@ let config_enable_writable_misa = ref true
let config_enable_dirty_update = ref false
let config_enable_misaligned_access = ref false
let config_mtval_has_illegal_inst_bits = ref false
-let config_enable_svinval = ref false
+let config_enable_svinval = ref false
let config_enable_zcb = ref false
let config_enable_writable_fiom = ref true
let config_enable_vext = ref true
@@ -90,7 +90,7 @@ let enable_vext () = !config_enable_vext
let enable_dirty_update () = !config_enable_dirty_update
let enable_misaligned_access () = !config_enable_misaligned_access
let mtval_has_illegal_inst_bits () = !config_mtval_has_illegal_inst_bits
-let enable_svinval () = !config_enable_svinval
+let enable_svinval () = !config_enable_svinval
let enable_zcb () = !config_enable_zcb
let enable_zfinx () = false
let enable_writable_fiom () = !config_enable_writable_fiom