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| author | Ved Shanbhogue <91900059+ved-rivos@users.noreply.github.com> | 2024-06-14 03:39:32 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-06-14 09:39:32 +0100 |
| commit | 0e9850fed5bee44346e583f334c6e2a6a25d5cd3 (patch) | |
| tree | e903ec6f5a5ffaa16e4896832c484015675158f4 | |
| parent | 575d865b80c5c760cb266bf0908b12e21cf30185 (diff) | |
| download | sail-riscv-0e9850fed5bee44346e583f334c6e2a6a25d5cd3.zip sail-riscv-0e9850fed5bee44346e583f334c6e2a6a25d5cd3.tar.gz sail-riscv-0e9850fed5bee44346e583f334c6e2a6a25d5cd3.tar.bz2 | |
Add Zaamo and Zalrsc
These are sub-extensions for AMO and LR/SC support. Currently hard-coded to be the same as overall atomic support.
Specification: https://github.com/ved-rivos/riscv-zaamo-zalrsc
| -rw-r--r-- | model/riscv_insts_aext.sail | 12 | ||||
| -rw-r--r-- | model/riscv_sys_regs.sail | 4 |
2 files changed, 10 insertions, 6 deletions
diff --git a/model/riscv_insts_aext.sail b/model/riscv_insts_aext.sail index 00bf0d1..3bf44b8 100644 --- a/model/riscv_insts_aext.sail +++ b/model/riscv_insts_aext.sail @@ -43,8 +43,8 @@ function amo_width_valid(size : word_width) -> bool = { /* ****************************************************************** */ union clause ast = LOADRES : (bool, bool, regidx, word_width, regidx) -mapping clause encdec = LOADRES(aq, rl, rs1, size, rd) if haveAtomics() & amo_width_valid(size) - <-> 0b00010 @ bool_bits(aq) @ bool_bits(rl) @ 0b00000 @ rs1 @ 0b0 @ size_enc(size) @ rd @ 0b0101111 if haveAtomics() & amo_width_valid(size) +mapping clause encdec = LOADRES(aq, rl, rs1, size, rd) if haveZalrsc() & amo_width_valid(size) + <-> 0b00010 @ bool_bits(aq) @ bool_bits(rl) @ 0b00000 @ rs1 @ 0b0 @ size_enc(size) @ rd @ 0b0101111 if haveZalrsc() & amo_width_valid(size) /* We could set load-reservations on physical or virtual addresses. @@ -88,8 +88,8 @@ mapping clause assembly = LOADRES(aq, rl, rs1, size, rd) /* ****************************************************************** */ union clause ast = STORECON : (bool, bool, regidx, regidx, word_width, regidx) -mapping clause encdec = STORECON(aq, rl, rs2, rs1, size, rd) if haveAtomics() & amo_width_valid(size) - <-> 0b00011 @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_enc(size) @ rd @ 0b0101111 if haveAtomics() & amo_width_valid(size) +mapping clause encdec = STORECON(aq, rl, rs2, rs1, size, rd) if haveZalrsc() & amo_width_valid(size) + <-> 0b00011 @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_enc(size) @ rd @ 0b0101111 if haveZalrsc() & amo_width_valid(size) /* NOTE: Currently, we only EA if address translation is successful. This may need revisiting. */ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = { @@ -163,8 +163,8 @@ mapping encdec_amoop : amoop <-> bits(5) = { AMOMAXU <-> 0b11100 } -mapping clause encdec = AMO(op, aq, rl, rs2, rs1, size, rd) if haveAtomics() & amo_width_valid(size) - <-> encdec_amoop(op) @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_enc(size) @ rd @ 0b0101111 if haveAtomics() & amo_width_valid(size) +mapping clause encdec = AMO(op, aq, rl, rs2, rs1, size, rd) if haveZaamo() & amo_width_valid(size) + <-> encdec_amoop(op) @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_enc(size) @ rd @ 0b0101111 if haveZaamo() & amo_width_valid(size) /* NOTE: Currently, we only EA if address translation is successful. This may need revisiting. */ diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index 6c66492..3537abc 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -161,6 +161,10 @@ function haveZknd() -> bool = true function haveZmmul() -> bool = true +/* A extension sub-extensions */ +function haveZaamo() -> bool = haveAtomics() +function haveZalrsc() -> bool = haveAtomics() + /* Zicond extension support */ function haveZicond() -> bool = true |