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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-10 10:06:09 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-10 10:06:09 -0700 |
| commit | 0bf06ac7f9659cfcca032136563c5b5b3ce473cb (patch) | |
| tree | 4eb11145af5d6bdab36789c8efdd96ec86695fd3 | |
| parent | ac2d819ad9f7fa42dcd8a3b36f45329a809b4414 (diff) | |
| parent | 4be9ddcc001db052093915515bd9d1ccab86d9cf (diff) | |
| download | sail-riscv-0bf06ac7f9659cfcca032136563c5b5b3ce473cb.zip sail-riscv-0bf06ac7f9659cfcca032136563c5b5b3ce473cb.tar.gz sail-riscv-0bf06ac7f9659cfcca032136563c5b5b3ce473cb.tar.bz2 | |
Merge pull request #6 from jrtc27/asm-load-store-imm
Print canonical assembly for immediate loads/stores
| -rw-r--r-- | model/riscv_insts_base.sail | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail index 7ac4294..6bb3050 100644 --- a/model/riscv_insts_base.sail +++ b/model/riscv_insts_base.sail @@ -358,7 +358,7 @@ mapping maybe_u = { } mapping clause assembly = LOAD(imm, rs1, rd, is_unsigned, size, aq, rl) - <-> "l" ^ size_mnemonic(size) ^ maybe_u(is_unsigned) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm) + <-> "l" ^ size_mnemonic(size) ^ maybe_u(is_unsigned) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_12(imm) ^ opt_spc() ^ "(" ^ opt_spc() ^ reg_name(rs1) ^ opt_spc() ^ ")" /* ****************************************************************** */ union clause ast = STORE : (bits(12), regbits, regbits, word_width, bool, bool) @@ -408,8 +408,8 @@ function clause execute (STORE(imm, rs2, rs1, width, aq, rl)) = { } } -mapping clause assembly = STORE(imm, rs1, rd, size, aq, rl) - <-> "s" ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm) +mapping clause assembly = STORE(imm, rs2, rs1, size, aq, rl) + <-> "s" ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_12(imm) ^ opt_spc() ^ "(" ^ opt_spc() ^ reg_name(rs1) ^ opt_spc() ^ ")" /* ****************************************************************** */ union clause ast = ADDIW : (bits(12), regbits, regbits) |