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| author | Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu> | 2023-02-27 12:36:17 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-03-09 18:30:21 +0100 |
| commit | a7af3b3c135899712bc9253c054cd407c7f842d4 (patch) | |
| tree | 98cdf6e5ab73b7eecf9dfdf4618ddaafb333489f | |
| parent | a9dec67897fda09f727bd2e8c2970083d7e04ad9 (diff) | |
| download | sail-riscv-zfa.zip sail-riscv-zfa.tar.gz sail-riscv-zfa.tar.bz2 | |
Zfa: Implement FCVTMOD.W.Dzfa
The FCVTMOD.W.D instruction is defined similarly to the FCVT.W.D instruction,
with the following differences:
* FCVTMOD.W.D always rounds towards zero.
* Bits 31:0 are taken from the rounded, unbounded two's complement result,
then sign-extended to XLEN bits and written to integer register rd.
* Positive infinity, negative infinity and NaN are converted to zero.
Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
| -rw-r--r-- | model/riscv_insts_zfa.sail | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/model/riscv_insts_zfa.sail b/model/riscv_insts_zfa.sail index 352c5e5..cca09f8 100644 --- a/model/riscv_insts_zfa.sail +++ b/model/riscv_insts_zfa.sail @@ -739,3 +739,32 @@ function clause execute(RISCV_FLTQ_D(rs2, rs1, rd)) = { X(rd) = EXTZ(bool_to_bits(rd_val)); RETIRE_SUCCESS } + +/* FCVTMOD.W.D */ + +union clause ast = RISCV_FCVTMOD_W_D : (regidx, regidx) + +/* We need rounding mode to be explicitly specified to RTZ(0b001) */ +mapping clause encdec = RISCV_FCVTMOD_W_D(rs1, rd) if (haveDExt() & haveZfa()) + <-> 0b110_0001 @ 0b01000 @ rs1 @ 0b001 @ rd @ 0b101_0011 if (haveDExt() & haveZfa()) + +mapping clause assembly = RISCV_FCVTMOD_W_D(rs1, rd) + <-> "fcvtmod.w.d" ^ spc() ^ reg_name(rd) + ^ spc() ^ freg_name(rs1) + +function clause execute(RISCV_FCVTMOD_W_D(rs1, rd)) = { + let rs1_val_D = F(rs1); + + let (fflags, rd_val_temp) = riscv_f64ToI32(0b001, rs1_val_D); + + let rd_val :xlenbits = + if (f_is_NaN_D(rs1_val_D) | + f_is_pos_inf_D(rs1_val_D) | + f_is_neg_inf_D(rs1_val_D)) + then EXTS(0b0) + else EXTS(rd_val_temp[31..0]); + + write_fflags(fflags); + X(rd) = rd_val; + RETIRE_SUCCESS +}
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