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author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-04-29 16:32:58 -0700 |
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committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-04-29 16:32:58 -0700 |
commit | ef0e8aac2b738a1b6e7e8d6ff485dfda5f5c0ba8 (patch) | |
tree | 06db68045f08ad10cbc18b48705ac74ec79a1eee | |
parent | f14e8ebac39bf6771f0d1775d5145f7f6549c5ea (diff) | |
download | sail-riscv-ef0e8aac2b738a1b6e7e8d6ff485dfda5f5c0ba8.zip sail-riscv-ef0e8aac2b738a1b6e7e8d6ff485dfda5f5c0ba8.tar.gz sail-riscv-ef0e8aac2b738a1b6e7e8d6ff485dfda5f5c0ba8.tar.bz2 |
Update docs for previous commits.
-rw-r--r-- | doc/ExtendingGuide.md | 7 | ||||
-rw-r--r-- | doc/ReadingGuide.md | 10 | ||||
-rw-r--r-- | model/riscv_decode_ext.sail | 9 |
3 files changed, 19 insertions, 7 deletions
diff --git a/doc/ExtendingGuide.md b/doc/ExtendingGuide.md index f38130a..4533b8b 100644 --- a/doc/ExtendingGuide.md +++ b/doc/ExtendingGuide.md @@ -103,6 +103,13 @@ examples on how this can done. These instruction definitions can access any newly defined architectural state and perform virtual or physical memory accesses as is done in `riscv.sail`. +Interposing on instruction decode +--------------------------------- + +An extension may wish to check and transform a decoded instruction. +This is supported via a post-decode extension hook, the default +implementation of which is provided in `riscv_decode_ext.sail`. + General guidelines ------------------ diff --git a/doc/ReadingGuide.md b/doc/ReadingGuide.md index 9145ac9..5c7e656 100644 --- a/doc/ReadingGuide.md +++ b/doc/ReadingGuide.md @@ -90,11 +90,11 @@ The model contains the following Sail modules in the `model` directory: - `riscv_step.sail` implements the top-level fetch and execute loop. The `fetch` is done in 16-bit granules to handle RVC instructions. The `step` function performs the instruction fetch, handles any - fetch errors, dispatches the execution of each instruction, and - checks for any pending interrupts that may need to be handled. A - `loop` function implements the execute loop, and uses the same HTIF - (host-target interface) mechanism as the Spike emulator to detect - termination of execution. + fetch errors, decodes the fetched value, dispatches the execution of + the decoded instruction, and checks for any pending interrupts that may + need to be handled. A `loop` function implements the execute loop, + and uses the same HTIF (host-target interface) mechanism as the + Spike emulator to detect termination of execution. - `riscv_analysis.sail` is used in the formal operational RVWMO memory model. diff --git a/model/riscv_decode_ext.sail b/model/riscv_decode_ext.sail index 2f4c5af..2a48399 100644 --- a/model/riscv_decode_ext.sail +++ b/model/riscv_decode_ext.sail @@ -1,2 +1,7 @@ -/* Default (identity) implementation of post decode hook. */ -function ext_post_decode_hook(x) = x
\ No newline at end of file +/* Extensions may wish to interpose and transform decoded instructions, + * based on other machine state. This is supported via a post-decode + * instruction hook, the default implementation of which is provided below. + */ + +val ext_post_decode_hook : ast -> ast effect {rreg} +function ext_post_decode_hook(x) = x |