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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-03-04 13:13:39 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-03-04 13:14:00 -0800 |
| commit | a6e01eb4f5e2df4933e5884723f05896d4c57bba (patch) | |
| tree | cccb1b0c84e67eed15cfb0d40ece139cf6e4e15c | |
| parent | 5201dccd129055f2a32952d4e96d7ecf6f41d174 (diff) | |
| download | sail-riscv-a6e01eb4f5e2df4933e5884723f05896d4c57bba.zip sail-riscv-a6e01eb4f5e2df4933e5884723f05896d4c57bba.tar.gz sail-riscv-a6e01eb4f5e2df4933e5884723f05896d4c57bba.tar.bz2 | |
Fix missed RV32 check for shamt in sll/srl.
| -rw-r--r-- | model/riscv_insts_base.sail | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail index c612039..87da930 100644 --- a/model/riscv_insts_base.sail +++ b/model/riscv_insts_base.sail @@ -185,11 +185,15 @@ mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRAI) <-> 0b010000 @ sham function clause execute (SHIFTIOP(shamt, rs1, rd, op)) = { let rs1_val = X(rs1); + /* the decoder guard should ensure that shamt[5] = 0 for RV32 */ let result : xlenbits = match op { - RISCV_SLLI => rs1_val << shamt, - RISCV_SRLI => rs1_val >> shamt, + RISCV_SLLI => if sizeof(xlen) == 32 + then rs1_val << shamt[4..0] + else rs1_val << shamt, + RISCV_SRLI => if sizeof(xlen) == 32 + then rs1_val >> shamt[4..0] + else rs1_val >> shamt, RISCV_SRAI => if sizeof(xlen) == 32 - /* the decoder guard should ensure that shamt[5] = 0 for RV32 */ then shift_right_arith32(rs1_val, shamt[4..0]) else shift_right_arith64(rs1_val, shamt) }; @@ -230,8 +234,12 @@ function clause execute (RTYPE(rs2, rs1, rd, op)) = { RISCV_AND => rs1_val & rs2_val, RISCV_OR => rs1_val | rs2_val, RISCV_XOR => rs1_val ^ rs2_val, - RISCV_SLL => rs1_val << (rs2_val[5..0]), - RISCV_SRL => rs1_val >> (rs2_val[5..0]), + RISCV_SLL => if sizeof(xlen) == 32 + then rs1_val << (rs2_val[4..0]) + else rs1_val << (rs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then rs1_val >> (rs2_val[4..0]) + else rs1_val >> (rs2_val[5..0]), RISCV_SUB => rs1_val - rs2_val, RISCV_SRA => if sizeof(xlen) == 32 then shift_right_arith32(rs1_val, rs2_val[4..0]) |