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| author | Jessica Clarke <jrtc27@jrtc27.com> | 2022-11-01 18:59:39 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-11-01 18:59:39 +0000 |
| commit | 4d05aa1698a0003a4f6f99e1380c743711c32052 (patch) | |
| tree | a4182a4b188f1b4a6e2e5ac5162a98e232dbc620 | |
| parent | 5cc5a93c2b05a3839230bfba532d9bd75c0ff5b0 (diff) | |
| download | sail-riscv-cookbook_br.zip sail-riscv-cookbook_br.tar.gz sail-riscv-cookbook_br.tar.bz2 | |
riscv_step: Fix -i/--mtval-has-illegal-inst-bits option (#174)cookbook_br
This option causes handle_illegal to pass instbits as the value to set
for xtval, but instbits is never set so it ends up being 0 just as if
the option was never enabled. Fix this by initialising instbits during
fetch; we could make this conditional on whether the option is enabled
but that seems unnecessary and introduces tighter coupling.
Note that this option appears to have always been broken; when it was
originally added, instbits was only written two in two cases which were
both dead code and later removed in eb176111887b.
Closes: #173
| -rw-r--r-- | model/riscv_step.sail | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/model/riscv_step.sail b/model/riscv_step.sail index 8e94c16..40c0c80 100644 --- a/model/riscv_step.sail +++ b/model/riscv_step.sail @@ -98,6 +98,7 @@ function step(step_no : int) -> bool = { }, /* non-error cases: */ F_RVC(h) => { + instbits = EXTZ(h); let ast = decodeCompressed(h); if get_config_print_instr() then { @@ -113,6 +114,7 @@ function step(step_no : int) -> bool = { } }, F_Base(w) => { + instbits = EXTZ(w); let ast = decode(w); if get_config_print_instr() then { |