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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Texas Instruments DaVinci family: TMS320DM355
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME dm355
}
# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
# after JTAG reset until ICEpick is used to route them in.
set EMU01 "-disable"
# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
# needing any ICEpick interaction.
#set EMU01 "-enable"
source [find target/icepick.cfg]
#
# Also note: when running without RTCK before the PLLs are set up, you
# may need to slow the JTAG clock down quite a lot (under 2 MHz).
#
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID] } {
set _ETB_TAPID $ETB_TAPID
} else {
set _ETB_TAPID 0x2b900f0f
}
jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
if { [info exists CPU_TAPID] } {
set _CPU_TAPID $CPU_TAPID
} else {
set _CPU_TAPID 0x07926001
}
jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
# Primary TAP: ICEpick (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0b73b02f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
jtag configure $_CHIPNAME.jrc -event setup \
"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
################
# various symbol definitions, to avoid hard-wiring addresses
# and enable some sharing of DaVinci-family utility code
global dm355
set dm355 [ dict create ]
# Physical addresses for controllers and memory
# (Some of these are valid for many DaVinci family chips)
dict set dm355 sram0 0x00010000
dict set dm355 sram1 0x00014000
dict set dm355 sysbase 0x01c40000
dict set dm355 pllc1 0x01c40800
dict set dm355 pllc2 0x01c40c00
dict set dm355 psc 0x01c41000
dict set dm355 gpio 0x01c67000
dict set dm355 a_emif 0x01e10000
dict set dm355 a_emif_cs0 0x02000000
dict set dm355 a_emif_cs1 0x04000000
dict set dm355 ddr_emif 0x20000000
dict set dm355 ddr 0x80000000
dict set dm355 uart0 0x01c20000
dict set dm355 uart1 0x01c20400
dict set dm355 uart2 0x01e06000
source [find target/davinci.cfg]
################
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
# and the ETB memory (4K) are other options, while trace is unused.
set _TARGETNAME $_CHIPNAME.arm
target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
# and that the work area is used only with a kernel mmu context ...
$_TARGETNAME configure \
-work-area-virt [expr {0xfffe0000 + 0x4000}] \
-work-area-phys [dict get $dm355 sram1] \
-work-area-size 0x4000 \
-work-area-backup 0
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
adapter speed 1500
$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
# trace setup
etm config $_TARGETNAME 16 normal full etb
etb config $_TARGETNAME $_CHIPNAME.etb
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