blob: b6d9a22a2c03a37d512737d567814e935e3bca0f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
|
# SPDX-License-Identifier: GPL-2.0-or-later
# script for stm32g0x family
#
# stm32g0 devices support SWD transports only.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME stm32g0x
}
set _ENDIAN little
# Work-area is a space in RAM used for flash programming
# Smallest proposed target has 8kB ram, use 4kB by default to avoid surprises
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x1000
}
#jtag scan chain
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
# Section 37.5.5 - corresponds to Cortex-M0+
set _CPUTAPID 0x0bc11477
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
# reasonable default
adapter speed 2000
adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
reset_config srst_nogate
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
proc stm32g0x_default_reset_start {} {
# Reset clock is HSI16 (16 MHz)
adapter speed 2000
}
proc stm32g0x_default_examine_end {} {
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
mmw 0x40015804 0x00000006 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0x40015808 0x00001800 0
}
proc stm32g0x_default_reset_init {} {
# Increase clock to 64 Mhz
mmw 0x40022000 0x00000002 0x00000005 ;# FLASH_ACR: Latency = 2
mww 0x4002100C 0x30000802 ;# RCC_PLLCFGR = PLLR=/2, PLLN=8, PLLM=/1, PLLSRC=0x2
mmw 0x40021000 0x01000000 0x00000000 ;# RCC_CR |= PLLON
mmw 0x40021008 0x00000002 0x00000005 ;# RCC_CFGR: SW=PLLRCLK
# Boost JTAG frequency
adapter speed 4000
}
# Default hooks
$_TARGETNAME configure -event examine-end { stm32g0x_default_examine_end }
$_TARGETNAME configure -event reset-start { stm32g0x_default_reset_start }
$_TARGETNAME configure -event reset-init { stm32g0x_default_reset_init }
|
