blob: 1561d7303eb5626d404c0de161b6ae9759168087 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
|
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME pic32mx
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
# force an error till we get a good number
set _CPUTAPID 0x30938053
}
jtag_nsrst_delay 100
jtag_ntrst_delay 100
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config srst_only
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size 16384 -work-area-backup 0
$_TARGETNAME configure -event reset-init {
#
# from reset the pic32 cannot execute code in ram - enable ram execution
# minimum offset from start of ram is 2k
#
# BMXCON
mww 0xbf882000 0x001f0040
# BMXDKPBA: 0xa0000800
mww 0xbf882010 0x00000800
# BMXDUDBA
mww 0xbf882020 0x00004000
# BMXDUPBA
mww 0xbf882030 0x00004000
}
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME pic32mx 0xbd000000 0 0 0 $_TARGETNAME
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME pic32mx 0xbfc00000 0 0 0 $_TARGETNAME
# For more information about the configuration files, take a look at:
# openocd.texi
|
