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# SPDX-License-Identifier: GPL-2.0-or-later
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lpc2900
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x0596802B
}
if { [info exists HAS_ETB] } {
} else {
# Set default (no ETB).
# Show a warning, because this should have been configured explicitly.
set HAS_ETB 0
# TODO: warning?
}
if { [info exists ETBTAPID] } {
set _ETBTAPID $ETBTAPID
} else {
set _ETBTAPID 0x1B900F0F
}
# TRST and SRST both exist, and can be controlled independently
reset_config trst_and_srst separate
# Define the _TARGETNAME
set _TARGETNAME $_CHIPNAME.cpu
# Include the ETB tap controller if asked for.
# Has to be done manually for newer devices (not an "old" LPC2917/2919).
if { $HAS_ETB == 1 } {
# Clear the HAS_ETB flag. Must be set again for a new tap in the chain.
set HAS_ETB 0
# Add the ETB tap controller and the ARM9 core debug tap
jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
# Create the ".cpu" target
target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
# Configure ETM and ETB
etm config $_TARGETNAME 8 normal full etb
etb config $_TARGETNAME $_CHIPNAME.etb
} else {
# Add the ARM9 core debug tap
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
# Create the ".cpu" target
target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
}
arm7_9 dbgrq enable
arm7_9 dcc_downloads enable
# Flash bank configuration:
# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>
# Flash base address, total flash size, and number of sectors are all configured automatically.
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
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