blob: d3fae8a9b0601683a895e6afc1ad43fb4625e443 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
|
#
# Freescale i.MX6SoloX
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME imx6sx
}
# 2x CoreSight Debug Access Port for Cortex-M4 and Cortex-A9
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME cpu_m4 -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
dap create $_CHIPNAME.dap_m4 -chain-position $_CHIPNAME.cpu_m4
jtag newtap $_CHIPNAME cpu_a9 -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
dap create $_CHIPNAME.dap_a9 -chain-position $_CHIPNAME.cpu_a9
# SDMA / no IDCODE
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
# System JTAG Controller
if { [info exists SJC_TAPID] } {
set _SJC_TAPID $SJC_TAPID
} else {
set _SJC_TAPID 0x0891c01d
}
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
-expected-id $_SJC_TAPID -ignore-version
# Cortex-A9 (boot core)
target create $_CHIPNAME.cpu_a9 cortex_a -dap $_CHIPNAME.dap_a9 \
-coreid 0 -dbgbase 0x82150000
# Cortex-M4 (default off)
target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap_m4 \
-ap-num 0 -defer-examine
# AHB mem-ap target
target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap_a9 -ap-num 0
# Default target is Cortex-A9
targets $_CHIPNAME.cpu_a9
|
