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# SPDX-License-Identifier: GPL-2.0-or-later
# Cadence virtual debug interface
# RISCV swerv core with Swerv through JTAG
source [find interface/vdebug.cfg]
set _CHIPNAME rv32
set _HARTID 0x00
set _CPUTAPID 0x1000008b
set _MEMSTART 0x00000000
set _MEMSIZE 0x10000
# vdebug select transport
transport select jtag
# JTAG reset config, frequency and reset delay
reset_config trst_and_srst
adapter speed 50000
adapter srst delay 5
# BFM hierarchical path and input clk period
vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
# DMA Memories to access backdoor (up to 4)
vdebug mem_path tbench.i_ahb_ic.mem $_MEMSTART $_MEMSIZE
# need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id $_CPUTAPID
jtag arp_init-reset
source [find target/vd_riscv.cfg]
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