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# SPDX-License-Identifier: GPL-2.0-or-later
# Cadence virtual debug interface
# Arm Cortex A53x2 through JTAG
source [find interface/vdebug.cfg]
set CORES 2
set CHIPNAME a53
set ACCESSPORT 0
set MEMSTART 0x00000000
set MEMSIZE 0x1000000
set DBGBASE {0x80810000 0x80910000}
set CTIBASE {0x80820000 0x80920000}
set CPUTAPID 0x5ba00477
# vdebug select transport
transport select jtag
# JTAG reset config, frequency and reset delay
reset_config trst_and_srst
adapter speed 50000
adapter srst delay 5
# BFM hierarchical path and input clk period
vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
# DMA Memories to access backdoor (up to 20)
vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE
jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
jtag arp_init-reset
source [find target/vd_aarch64.cfg]
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