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# SPDX-License-Identifier: GPL-2.0-or-later
# This is an STM32F723E discovery board with a single STM32F723IEK6 chip.
# http://www.st.com/en/evaluation-tools/32f723ediscovery.html
# This is for using the onboard STLINK
source [find interface/stlink.cfg]
transport select hla_swd
# increase working area to 128KB
set WORKAREASIZE 0x20000
# enable stmqspi
set QUADSPI 1
source [find target/stm32f7x.cfg]
reset_config srst_only
# QUADSPI initialization
proc qspi_init { } {
global a
mmw 0x40023830 0x000007FF 0 ;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
mmw 0x40023838 0x00000002 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock)
sleep 1 ;# Wait for clock startup
# PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PC10: BK1_IO1, PC09: BK1_IO0
# PB06:AF10:V, PB02:AF09:V, PC10:AF09:V, PC09:AF09:V, PD13:AF09:V, PE02:AF09:V
# Port B: PB06:AF10:V, PB02:AF09:V
mmw 0x40020400 0x00002020 0x00001010 ;# MODER
mmw 0x40020408 0x00003030 0x00000000 ;# OSPEEDR
mmw 0x40020420 0x0A000900 0x05000600 ;# AFRL
# Port C: PC10:AF09:V, PC09:AF09:V
mmw 0x40020800 0x00280000 0x00140000 ;# MODER
mmw 0x40020808 0x003C0000 0x00000000 ;# OSPEEDR
mmw 0x40020824 0x00000990 0x00000660 ;# AFRH
# Port D: PD13:AF09:V
mmw 0x40020C00 0x08000000 0x04000000 ;# MODER
mmw 0x40020C08 0x0C000000 0x00000000 ;# OSPEEDR
mmw 0x40020C24 0x00900000 0x00600000 ;# AFRH
# Port E: PE02:AF09:V
mmw 0x40021000 0x00000020 0x00000010 ;# MODER
mmw 0x40021008 0x00000030 0x00000000 ;# OSPEEDR
mmw 0x40021020 0x00000900 0x00000600 ;# AFRL
mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
mww 0xA0001000 0x03500008 ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
mww 0xA0001004 0x00190100 ;# QUADSPI_DCR: FSIZE=0x19, CSHT=0x01, CKMODE=0
mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1
# 1-line spi mode
mww 0xA0001014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
sleep 1
# memory-mapped read mode with 4-byte addresses
mww 0xA0001014 0x0D003513 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
}
$_TARGETNAME configure -event reset-init {
mww 0x40023C00 0x00000006 ;# 6 WS for 192 MHz HCLK
sleep 1
mww 0x40023804 0x24003008 ;# 192 MHz: PLLM=8, PLLN=192, PLLP=2
mww 0x40023808 0x00009400 ;# APB1: /4, APB2: /2
mmw 0x40023800 0x01000000 0x00000000 ;# PLL on
sleep 1
mmw 0x40023808 0x00000002 0x00000000 ;# switch to PLL
sleep 1
adapter speed 4000
qspi_init
}
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