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# Marvell OpenRD
source [find interface/openrd.cfg]
source [find target/feroceon.cfg]
$_TARGETNAME configure \
-work-area-phys 0x10000000 \
-work-area-size 65536 \
-work-area-backup 0
arm7_9 dcc_downloads enable
# this assumes the hardware default peripherals location before u-Boot moves it
nand device orion 0 0xd8000000
proc openrd_init { } {
# We need to assert DBGRQ while holding nSRST down.
# However DBGACK will be set only when nSRST is released.
# Furthermore, the JTAG interface doesn't respond at all when
# the CPU is in the WFI (wait for interrupts) state, so it is
# possible that initial tap examination failed. So let's
# re-examine the target again here when nSRST is asserted which
# should then succeed.
jtag_reset 0 1
feroceon.cpu arp_examine
halt 0
jtag_reset 0 0
wait_halt
arm926ejs cp15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x37543000 # Dunit Control Low Register
mww 0xD0001408 0x22125451 # DDR SDRAM Timing (Low) Register
mww 0xD000140C 0x00000A33 # DDR SDRAM Timing (High) Register
mww 0xD0001410 0x000000CC # DDR SDRAM Address Control Register
mww 0xD0001414 0x00000000 # DDR SDRAM Open Pages Control Register
mww 0xD0001418 0x00000000 # DDR SDRAM Operation Register
mww 0xD000141C 0x00000C52 # DDR SDRAM Mode Register
mww 0xD0001420 0x00000004 # DDR SDRAM Extended Mode Register
mww 0xD0001424 0x0000F17F # Dunit Control High Register
mww 0xD0001428 0x00085520 # Dunit Control High Register
mww 0xD000147c 0x00008552 # Dunit Control High Register
mww 0xD0001504 0x0FFFFFF1 # CS0n Size Register
mww 0xD0001508 0x10000000 # CS1n Base Register
mww 0xD000150C 0x0FFFFFF5 # CS1n Size Register
mww 0xD0001514 0x00000000 # CS2n Size Register
mww 0xD000151C 0x00000000 # CS3n Size Register
mww 0xD0001494 0x00120012 # DDR2 SDRAM ODT Control (Low) Register
mww 0xD0001498 0x00000000 # DDR2 SDRAM ODT Control (High) REgister
mww 0xD000149C 0x0000E40F # DDR2 Dunit ODT Control Register
mww 0xD0001480 0x00000001 # DDR SDRAM Initialization Control Register
mww 0xD0020204 0x00000000 # Main IRQ Interrupt Mask Register
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # "
mww 0xD0010000 0x01111111 # MPP 0 to 7
mww 0xD0010004 0x11113322 # MPP 8 to 15
mww 0xD0010008 0x00001111 # MPP 16 to 23
mww 0xD0010418 0x003E07CF # NAND Read Parameters REgister
mww 0xD001041C 0x000F0F0F # NAND Write Parameters Register
mww 0xD0010470 0x01C7D943 # NAND Flash Control Register
}
proc openrd_reflash_uboot { } {
# reflash the u-Boot binary and reboot into it
openrd_init
nand probe 0
nand erase 0 0x0 0xa0000
nand write 0 uboot.bin 0 oob_softecc_kw
resume
}
proc openrd_load_uboot { } {
# load u-Boot into RAM and execute it
openrd_init
load_image uboot.elf
verify_image uboot.elf
resume 0x00600000
}
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