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# SPDX-License-Identifier: GPL-2.0-or-later
source [find target/alphascale_asm9260t.cfg]
reset_config trst_and_srst
$_TARGETNAME configure -event reset-init {
echo "Configure clock"
# Enable SRAM clk
mww 0x80040024 0x4
# Enable IRQ clk
mww 0x80040034 0x100
# Enable DMA0,1 clk
mww 0x80040024 0x600
# Make sysre syspll is enabled
mww 0x80040238 0x750
#CPU = PLLCLK/2
mww 0x8004017C 0x2
#SYSAHBCLK = CPUCLK/2
mww 0x80040180 0x2
# Set PLL freq to 480MHz
mww 0x80040100 480
# normally we shoul waiting here until we get 0x1 (0x80040104)&0x1)==0x0)
sleep 100
# select PLL as main source
mww 0x80040120 0x1
# disable and enable main clk to update changes?
mww 0x80040124 0x0
mww 0x80040124 0x1
echo "Configure memory"
#enable EMI CLK
mww 0x80040024 0x40
# configure memory controller for internal SRAM
mww 0x80700000 0x1188
# change default emi clk delay
mww 0x8004034C 0xA0503
# make sure chip_select_register2_low has correct value (why?)
mww 0x8070001c 0x20000000
# set type to sdram and size to 32MB
mww 0x8070005c 0xa
# configure internal SDRAM timing
mww 0x80700004 0x024996d9
# configure Static Memory timing
mww 0x80700094 0x00542b4f
echo "Configure uart4"
# enable pinctrl clk
mww 0x80040024 0x2000000
# mux GPIO3_0 and GPIO3_1 to UART4
mww 0x80044060 0x2
mww 0x80044064 0x2
# configure UART4CLKDIV
mww 0x800401a8 0x1
# enable uart4 clk
mww 0x80040024 0x8000
# clear softrst and clkgate on uart4
mww 0x80010008 0xC0000000
# set bandrate 115200 12M
mww 0x80010030 0x00062070
# enable Rx&Tx
mww 0x80010024 0x301
# clear hw control
mww 0x80010028 0xc000
}
$_TARGETNAME configure -work-area-phys 0x21ffe000 -work-area-virt 0xc1ffe000 -work-area-size 0x1000
$_TARGETNAME arm7_9 fast_memory_access enable
$_TARGETNAME arm7_9 dcc_downloads enable
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