1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
|
/*
* XMC1000 flash driver
*
* Copyright (c) 2016 Andreas Färber
*
* License: GPL-2.0+
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "imp.h"
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
#include <target/armv7m.h>
#define FLASH_BASE 0x10000000
#define PAU_BASE 0x40000000
#define SCU_BASE 0x40010000
#define NVM_BASE 0x40050000
#define FLASH_CS0 (FLASH_BASE + 0xf00)
#define PAU_FLSIZE (PAU_BASE + 0x404)
#define SCU_IDCHIP (SCU_BASE + 0x004)
#define NVMSTATUS (NVM_BASE + 0x00)
#define NVMPROG (NVM_BASE + 0x04)
#define NVMCONF (NVM_BASE + 0x08)
#define NVMSTATUS_BUSY (1 << 0)
#define NVMSTATUS_VERR_MASK (0x3 << 2)
#define NVMPROG_ACTION_OPTYPE_IDLE_VERIFY (0 << 0)
#define NVMPROG_ACTION_OPTYPE_WRITE (1 << 0)
#define NVMPROG_ACTION_OPTYPE_PAGE_ERASE (2 << 0)
#define NVMPROG_ACTION_ONE_SHOT_ONCE (1 << 4)
#define NVMPROG_ACTION_ONE_SHOT_CONTINUOUS (2 << 4)
#define NVMPROG_ACTION_VERIFY_EACH (1 << 6)
#define NVMPROG_ACTION_VERIFY_NO (2 << 6)
#define NVMPROG_ACTION_VERIFY_ARRAY (3 << 6)
#define NVMPROG_ACTION_IDLE 0x00
#define NVMPROG_ACTION_MASK 0xff
#define NVM_WORD_SIZE 4
#define NVM_BLOCK_SIZE (4 * NVM_WORD_SIZE)
#define NVM_PAGE_SIZE (16 * NVM_BLOCK_SIZE)
struct xmc1xxx_flash_bank {
bool probed;
};
static int xmc1xxx_nvm_set_idle(struct target *target)
{
return target_write_u16(target, NVMPROG, NVMPROG_ACTION_IDLE);
}
static int xmc1xxx_nvm_check_idle(struct target *target)
{
uint16_t val;
int retval;
retval = target_read_u16(target, NVMPROG, &val);
if (retval != ERROR_OK)
return retval;
if ((val & NVMPROG_ACTION_MASK) != NVMPROG_ACTION_IDLE) {
LOG_WARNING("NVMPROG.ACTION");
retval = xmc1xxx_nvm_set_idle(target);
}
return retval;
}
static int xmc1xxx_erase(struct flash_bank *bank, unsigned int first,
unsigned int last)
{
struct target *target = bank->target;
struct working_area *workarea;
struct reg_param reg_params[3];
struct armv7m_algorithm armv7m_algo;
unsigned i;
int retval;
const uint8_t erase_code[] = {
#include "../../../contrib/loaders/flash/xmc1xxx/erase.inc"
};
LOG_DEBUG("Infineon XMC1000 erase sectors %u to %u", first, last);
if (bank->target->state != TARGET_HALTED) {
LOG_WARNING("Cannot communicate... target not halted.");
return ERROR_TARGET_NOT_HALTED;
}
retval = xmc1xxx_nvm_check_idle(target);
if (retval != ERROR_OK)
return retval;
retval = target_alloc_working_area(target, sizeof(erase_code),
&workarea);
if (retval != ERROR_OK) {
LOG_ERROR("No working area available.");
retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
goto err_alloc_code;
}
retval = target_write_buffer(target, workarea->address,
sizeof(erase_code), erase_code);
if (retval != ERROR_OK)
goto err_write_code;
armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_algo.core_mode = ARM_MODE_THREAD;
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
buf_set_u32(reg_params[0].value, 0, 32, NVM_BASE);
buf_set_u32(reg_params[1].value, 0, 32, bank->base +
bank->sectors[first].offset);
buf_set_u32(reg_params[2].value, 0, 32, bank->base +
bank->sectors[last].offset + bank->sectors[last].size);
retval = target_run_algorithm(target,
0, NULL,
ARRAY_SIZE(reg_params), reg_params,
workarea->address, 0,
1000, &armv7m_algo);
if (retval != ERROR_OK) {
LOG_ERROR("Error executing flash sector erase "
"programming algorithm");
retval = xmc1xxx_nvm_set_idle(target);
if (retval != ERROR_OK)
LOG_WARNING("Couldn't restore NVMPROG.ACTION");
retval = ERROR_FLASH_OPERATION_FAILED;
goto err_run;
}
for (unsigned int sector = first; sector <= last; sector++)
bank->sectors[sector].is_erased = 1;
err_run:
for (i = 0; i < ARRAY_SIZE(reg_params); i++)
destroy_reg_param(®_params[i]);
err_write_code:
target_free_working_area(target, workarea);
err_alloc_code:
return retval;
}
static int xmc1xxx_erase_check(struct flash_bank *bank)
{
struct target *target = bank->target;
struct working_area *workarea;
struct reg_param reg_params[3];
struct armv7m_algorithm armv7m_algo;
uint16_t val;
unsigned i;
int retval;
const uint8_t erase_check_code[] = {
#include "../../../contrib/loaders/flash/xmc1xxx/erase_check.inc"
};
if (bank->target->state != TARGET_HALTED) {
LOG_WARNING("Cannot communicate... target not halted.");
return ERROR_TARGET_NOT_HALTED;
}
retval = target_alloc_working_area(target, sizeof(erase_check_code),
&workarea);
if (retval != ERROR_OK) {
LOG_ERROR("No working area available.");
retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
goto err_alloc_code;
}
retval = target_write_buffer(target, workarea->address,
sizeof(erase_check_code), erase_check_code);
if (retval != ERROR_OK)
goto err_write_code;
armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_algo.core_mode = ARM_MODE_THREAD;
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
buf_set_u32(reg_params[0].value, 0, 32, NVM_BASE);
for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
uint32_t start = bank->base + bank->sectors[sector].offset;
buf_set_u32(reg_params[1].value, 0, 32, start);
buf_set_u32(reg_params[2].value, 0, 32, start + bank->sectors[sector].size);
retval = xmc1xxx_nvm_check_idle(target);
if (retval != ERROR_OK)
goto err_nvmprog;
LOG_DEBUG("Erase-checking 0x%08" PRIx32, start);
retval = target_run_algorithm(target,
0, NULL,
ARRAY_SIZE(reg_params), reg_params,
workarea->address, 0,
1000, &armv7m_algo);
if (retval != ERROR_OK) {
LOG_ERROR("Error executing flash sector erase check "
"programming algorithm");
retval = xmc1xxx_nvm_set_idle(target);
if (retval != ERROR_OK)
LOG_WARNING("Couldn't restore NVMPROG.ACTION");
retval = ERROR_FLASH_OPERATION_FAILED;
goto err_run;
}
retval = target_read_u16(target, NVMSTATUS, &val);
if (retval != ERROR_OK) {
LOG_ERROR("Couldn't read NVMSTATUS");
goto err_nvmstatus;
}
bank->sectors[sector].is_erased = (val & NVMSTATUS_VERR_MASK) ? 0 : 1;
}
err_nvmstatus:
err_run:
err_nvmprog:
for (i = 0; i < ARRAY_SIZE(reg_params); i++)
destroy_reg_param(®_params[i]);
err_write_code:
target_free_working_area(target, workarea);
err_alloc_code:
return retval;
}
static int xmc1xxx_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t byte_count)
{
struct target *target = bank->target;
struct working_area *code_workarea, *data_workarea;
struct reg_param reg_params[4];
struct armv7m_algorithm armv7m_algo;
uint32_t block_count = DIV_ROUND_UP(byte_count, NVM_BLOCK_SIZE);
unsigned i;
int retval;
const uint8_t write_code[] = {
#include "../../../contrib/loaders/flash/xmc1xxx/write.inc"
};
LOG_DEBUG("Infineon XMC1000 write at 0x%08" PRIx32 " (%" PRIu32 " bytes)",
offset, byte_count);
if (offset & (NVM_BLOCK_SIZE - 1)) {
LOG_ERROR("offset 0x%" PRIx32 " breaks required block alignment",
offset);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
if (byte_count & (NVM_BLOCK_SIZE - 1)) {
LOG_WARNING("length %" PRIu32 " is not block aligned, rounding up",
byte_count);
}
if (target->state != TARGET_HALTED) {
LOG_WARNING("Cannot communicate... target not halted.");
return ERROR_TARGET_NOT_HALTED;
}
retval = target_alloc_working_area(target, sizeof(write_code),
&code_workarea);
if (retval != ERROR_OK) {
LOG_ERROR("No working area available for write code.");
retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
goto err_alloc_code;
}
retval = target_write_buffer(target, code_workarea->address,
sizeof(write_code), write_code);
if (retval != ERROR_OK)
goto err_write_code;
retval = target_alloc_working_area(target, MAX(NVM_BLOCK_SIZE,
MIN(block_count * NVM_BLOCK_SIZE, target_get_working_area_avail(target))),
&data_workarea);
if (retval != ERROR_OK) {
LOG_ERROR("No working area available for write data.");
retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
goto err_alloc_data;
}
armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_algo.core_mode = ARM_MODE_THREAD;
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
buf_set_u32(reg_params[0].value, 0, 32, NVM_BASE);
while (byte_count > 0) {
uint32_t blocks = MIN(block_count, data_workarea->size / NVM_BLOCK_SIZE);
uint32_t addr = bank->base + offset;
LOG_DEBUG("copying %" PRIu32 " bytes to SRAM " TARGET_ADDR_FMT,
MIN(blocks * NVM_BLOCK_SIZE, byte_count),
data_workarea->address);
retval = target_write_buffer(target, data_workarea->address,
MIN(blocks * NVM_BLOCK_SIZE, byte_count), buffer);
if (retval != ERROR_OK) {
LOG_ERROR("Error writing data buffer");
retval = ERROR_FLASH_OPERATION_FAILED;
goto err_write_data;
}
if (byte_count < blocks * NVM_BLOCK_SIZE) {
retval = target_write_memory(target,
data_workarea->address + byte_count, 1,
blocks * NVM_BLOCK_SIZE - byte_count,
&bank->default_padded_value);
if (retval != ERROR_OK) {
LOG_ERROR("Error writing data padding");
retval = ERROR_FLASH_OPERATION_FAILED;
goto err_write_pad;
}
}
LOG_DEBUG("writing 0x%08" PRIx32 "-0x%08" PRIx32 " (%" PRIu32 "x)",
addr, addr + blocks * NVM_BLOCK_SIZE - 1, blocks);
retval = xmc1xxx_nvm_check_idle(target);
if (retval != ERROR_OK)
goto err_nvmprog;
buf_set_u32(reg_params[1].value, 0, 32, addr);
buf_set_u32(reg_params[2].value, 0, 32, data_workarea->address);
buf_set_u32(reg_params[3].value, 0, 32, blocks);
retval = target_run_algorithm(target,
0, NULL,
ARRAY_SIZE(reg_params), reg_params,
code_workarea->address, 0,
5 * 60 * 1000, &armv7m_algo);
if (retval != ERROR_OK) {
LOG_ERROR("Error executing flash write "
"programming algorithm");
retval = xmc1xxx_nvm_set_idle(target);
if (retval != ERROR_OK)
LOG_WARNING("Couldn't restore NVMPROG.ACTION");
retval = ERROR_FLASH_OPERATION_FAILED;
goto err_run;
}
block_count -= blocks;
offset += blocks * NVM_BLOCK_SIZE;
buffer += blocks * NVM_BLOCK_SIZE;
byte_count -= MIN(blocks * NVM_BLOCK_SIZE, byte_count);
}
err_run:
err_nvmprog:
err_write_pad:
err_write_data:
for (i = 0; i < ARRAY_SIZE(reg_params); i++)
destroy_reg_param(®_params[i]);
target_free_working_area(target, data_workarea);
err_alloc_data:
err_write_code:
target_free_working_area(target, code_workarea);
err_alloc_code:
return retval;
}
static int xmc1xxx_protect_check(struct flash_bank *bank)
{
uint32_t nvmconf;
unsigned int num_protected;
int retval;
if (bank->target->state != TARGET_HALTED) {
LOG_WARNING("Cannot communicate... target not halted.");
return ERROR_TARGET_NOT_HALTED;
}
retval = target_read_u32(bank->target, NVMCONF, &nvmconf);
if (retval != ERROR_OK) {
LOG_ERROR("Cannot read NVMCONF register.");
return retval;
}
LOG_DEBUG("NVMCONF = %08" PRIx32, nvmconf);
num_protected = (nvmconf >> 4) & 0xff;
for (unsigned int i = 0; i < bank->num_sectors; i++)
bank->sectors[i].is_protected = (i < num_protected) ? 1 : 0;
return ERROR_OK;
}
static int xmc1xxx_get_info_command(struct flash_bank *bank, char *buf, int buf_size)
{
uint32_t chipid[8];
int i, retval;
if (bank->target->state != TARGET_HALTED) {
LOG_WARNING("Cannot communicate... target not halted.");
return ERROR_TARGET_NOT_HALTED;
}
/* Obtain the 8-word Chip Identification Number */
for (i = 0; i < 7; i++) {
retval = target_read_u32(bank->target, FLASH_CS0 + i * 4, &chipid[i]);
if (retval != ERROR_OK) {
LOG_ERROR("Cannot read CS0 register %i.", i);
return retval;
}
LOG_DEBUG("ID[%d] = %08" PRIX32, i, chipid[i]);
}
retval = target_read_u32(bank->target, SCU_BASE + 0x000, &chipid[7]);
if (retval != ERROR_OK) {
LOG_ERROR("Cannot read DBGROMID register.");
return retval;
}
LOG_DEBUG("ID[7] = %08" PRIX32, chipid[7]);
snprintf(buf, buf_size, "XMC%" PRIx32 "00 %" PRIX32 " flash %" PRIu32 "KB ROM %" PRIu32 "KB SRAM %" PRIu32 "KB",
(chipid[0] >> 12) & 0xff,
0xAA + (chipid[7] >> 28) - 1,
(((chipid[6] >> 12) & 0x3f) - 1) * 4,
(((chipid[4] >> 8) & 0x3f) * 256) / 1024,
(((chipid[5] >> 8) & 0x1f) * 256 * 4) / 1024);
return ERROR_OK;
}
static int xmc1xxx_probe(struct flash_bank *bank)
{
struct xmc1xxx_flash_bank *xmc_bank = bank->driver_priv;
uint32_t flash_addr = bank->base;
uint32_t idchip, flsize;
int retval;
if (xmc_bank->probed)
return ERROR_OK;
if (bank->target->state != TARGET_HALTED) {
LOG_WARNING("Cannot communicate... target not halted.");
return ERROR_TARGET_NOT_HALTED;
}
retval = target_read_u32(bank->target, SCU_IDCHIP, &idchip);
if (retval != ERROR_OK) {
LOG_ERROR("Cannot read IDCHIP register.");
return retval;
}
if ((idchip & 0xffff0000) != 0x10000) {
LOG_ERROR("IDCHIP register does not match XMC1xxx.");
return ERROR_FAIL;
}
LOG_DEBUG("IDCHIP = %08" PRIx32, idchip);
retval = target_read_u32(bank->target, PAU_FLSIZE, &flsize);
if (retval != ERROR_OK) {
LOG_ERROR("Cannot read FLSIZE register.");
return retval;
}
bank->num_sectors = 1 + ((flsize >> 12) & 0x3f) - 1;
bank->size = bank->num_sectors * 4 * 1024;
bank->sectors = calloc(bank->num_sectors,
sizeof(struct flash_sector));
for (unsigned int i = 0; i < bank->num_sectors; i++) {
if (i == 0) {
bank->sectors[i].size = 0x200;
bank->sectors[i].offset = 0xE00;
flash_addr += 0x1000;
} else {
bank->sectors[i].size = 4 * 1024;
bank->sectors[i].offset = flash_addr - bank->base;
flash_addr += bank->sectors[i].size;
}
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = -1;
}
xmc_bank->probed = true;
return ERROR_OK;
}
static int xmc1xxx_auto_probe(struct flash_bank *bank)
{
struct xmc1xxx_flash_bank *xmc_bank = bank->driver_priv;
if (xmc_bank->probed)
return ERROR_OK;
return xmc1xxx_probe(bank);
}
FLASH_BANK_COMMAND_HANDLER(xmc1xxx_flash_bank_command)
{
struct xmc1xxx_flash_bank *xmc_bank;
xmc_bank = malloc(sizeof(struct xmc1xxx_flash_bank));
if (!xmc_bank)
return ERROR_FLASH_OPERATION_FAILED;
xmc_bank->probed = false;
bank->driver_priv = xmc_bank;
return ERROR_OK;
}
static const struct command_registration xmc1xxx_exec_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
static const struct command_registration xmc1xxx_command_handlers[] = {
{
.name = "xmc1xxx",
.mode = COMMAND_ANY,
.help = "xmc1xxx flash command group",
.usage = "",
.chain = xmc1xxx_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
const struct flash_driver xmc1xxx_flash = {
.name = "xmc1xxx",
.commands = xmc1xxx_command_handlers,
.flash_bank_command = xmc1xxx_flash_bank_command,
.info = xmc1xxx_get_info_command,
.probe = xmc1xxx_probe,
.auto_probe = xmc1xxx_auto_probe,
.protect_check = xmc1xxx_protect_check,
.read = default_flash_read,
.erase = xmc1xxx_erase,
.erase_check = xmc1xxx_erase_check,
.write = xmc1xxx_write,
.free_driver_priv = default_flash_free_driver_priv,
};
|