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2018-04-09Merge branch 'master' into from_upstreamTim Newsome83-170/+1030
Conflicts: src/rtos/rtos.c src/rtos/rtos.h src/server/gdb_server.c Change-Id: Icd5a8165fe111f699542530c9cb034faf30e09b2
2018-03-30xilinx-dna.cfg: generic tools for reading Xilinx Device DNARobert Jordens3-0/+45
Most Xilinx FPGA devices contain an embedded, unique device identifier. The identifier is nonvolatile, permanently programmed into the FPGA, and is unchangeable providing a great serial / tracking number. This commit adds generic support for reading the Xilinx Spartan 6 and 7 Series (Kintex, Artix, Ultrascale) Device DNA. The code is similar to the function in fpga/xilinx-xc6s.cfg for Spartan 6 but the register addresses are different and the logic has been simplified. The code was not placed in xilinx-xc7.cfg. The approach of defining taps in the same file as library code to use them is fundamentally broken on boards that have more than one FPGA or other chips. This commit (like the addition of support for Xilinx XADC) starts to remedy that by splitting library code from board-specific fixed definitions. The support code is sourced in the Kasli and KC705 board support files as it was tested on these boards. Change-Id: Iba559c7c1b7e93e1270535fd9e6650007f3794da Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4396 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30tcl/fpga/xilinx-xadc.cfg: add support for XADCRobert Jordens3-0/+161
The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die temperature, internal power supply rail voltages as well as external voltages. The XADC is available both from fabric as well as through the JTAG TAP. This code implements access throught the JTAG TAP. https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf Change-Id: I6cef4d0244add71749fa28b58a736302151cc4dd Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4395 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30tcl/board: add support for KasliRobert Jordens1-0/+13
Kasli is an open hardware FPGA board. It is part of the Sinara family of devices designed to control quantum physics experiments (see Sayma_AMC for other boards already suppported by openocd). Kasli was developed as part of the opticlock project. It features a Xilinx Artix 7 100T FPGA, DDR3 RAM, a clock reconstruction and distribution network, four 6 Gb/s transceiver links (three SFP and one SATA) as well as interfaces to up to 12 Eurocard Extension Modules (EEMs). https://github.com/m-labs/sinara/wiki/Kasli http://www.opticlock.de/en/ Change-Id: I88b5e9f16b79e1e731056c45da6b5e1448d2c0e7 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4341 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30sayma_amc: add Sayma AMC board definitionRobert Jordens1-0/+45
Change-Id: I4a3dc5fe2d81b6906099af8cc1a360b3cf4a6b80 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4237 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30kcu105: add support for Xilinx KCU105Robert Jordens1-0/+11
* Development board with Kintex Ultrascale XCKU040 * Dual SPI 256 MBit flash, supported through xilinx_bscan_spi Change-Id: I478ec7481beedd270bfba8af56a93301b0ee3028 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4189 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30xilinx-xcu: add Xilinx Ultrascale tap dataRobert Jordens1-0/+72
The Ultrascale series is a bit more complicated to handle since with the stacked and interconnected dies the IR gets longer. This adds support for all currently known chips from the Ultrascale family. Change-Id: Ibac325dd6fadc76f73cc682b1c62c1a5f39f0786 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4188 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30target: restructure dap supportMatthias Welwarsky68-153/+235
- add 'dap create' command to create dap instances - move all dap subcmmand into the dap instance commands - keep 'dap info' for convenience - change all armv7 and armv8 targets to take a dap instance instead of a jtag chain position - restructure tap/dap/target relations, jtag tap no longer references the dap, daps are now independently created and initialized. - clean up swd connect - re-initialize DAP also on JTAG errors (e.g. after reset, power cycle) - update documentation - update target files Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4468 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30tcl/board: add configuration for the avnet ultrazed-eg starter kitMatthias Welwarsky2-0/+106
also contains target configuration for the Xilinx UltraScale+ platform Change-Id: I6300cbc85c1ed71df71d8aaca59500bbf18f0093 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4467 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30arm_cti: add cti command groupMatthias Welwarsky3-2/+13
Extend the CTI abstraction to be accessible from TCL and change the 'target' command to accept a cti 'object' instead of a base address. This also allows accessing CTI instances that are not related to a configured target. Change-Id: Iac9ed0edca6f1be00fe93783a35c26077f6bc80a Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4031 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-15tcl/target: warn if a Kinetis MCU is connected to a high level adapterTomas Vanek2-2/+27
Make sure the user is aware he can lock the device though unlock is not possible without access to MDM-AP. Change-Id: I92676530e95d19489c6739748a99c2895849f90f Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4403 Tested-by: jenkins
2018-03-13jtag: drivers: add support for FT232R sync bitbang JTAG interfacesMatej Kogovsek1-0/+2
Change-Id: Ib88a9e270f5c2a50902a137bcc97fdefd5aad1c6 Signed-off-by: Matej Kogovsek <matej@hamradio.si> Reviewed-on: http://openocd.zylin.com/4215 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-03-13tcl: interface: usb blaster I: specify driver explicitlyPaul Fertser1-0/+1
When a user asks for blaster I, he or she should either get it, or get an error, not blaster II driver. Change-Id: Ibc7683676ce42773e2b14ea5ccb3d119d1e6acea Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4381 Tested-by: jenkins
2018-03-12Add SWD protocol support to buspirate (2nd try)Mateusz Manowiecki1-1/+1
This is a second try for this patch. I removed the queues from the previous version. I made it compatible with SRST reset and added support for those features that could be supported in raw binary mode. Change-Id: I96fc06abbea9873e98b414f34afd9043fd9c2a41 Signed-off-by: Mateusz Manowiecki <segmentation@fault.pl> Reviewed-on: http://openocd.zylin.com/3960 Tested-by: jenkins Reviewed-by: Eric Work <work.eric@gmail.com> Reviewed-by: Thomas Jarosch <thomas.jarosch@intra2net.com> Reviewed-by: Jacob Alexander <haata@kiibohd.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-03-07pipistrello: decrease jtag speed to 10 MHzRobert Jordens1-1/+1
30 MHz is not working reliably here Change-Id: I38f5f8c7153fc64e313ee911b1629fb5f1114c39 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4242 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-03-07Added support for STMicroelectronics BlueNRG-1 and BlueNRG-2 SoCMichele Sardo3-0/+81
Added configuration files and flash loaders. Change-Id: I768eb3626f4e0eadb206bef90a867cc146fe8c75 Signed-off-by: Michele Sardo <msmttchr@gmail.com> Reviewed-on: http://openocd.zylin.com/4226 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-02-24efm32: Add JTAG definitions to EFM32 target fileJonas Norling1-3/+10
This makes it possible to program newer EFM32 and EFR32 chips with JTAG, as opposed to SWD. Change-Id: Ia3e8c1bbc66fc1f33e8cf2087ccf0d1b4dfd74e1 Signed-off-by: Jonas Norling <jonas.norling@cyanconnode.com> Reviewed-on: http://openocd.zylin.com/4262 Tested-by: jenkins Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-02-21icepick-d: extend access to core control registerMatthias Welwarsky1-6/+7
The ICEPick-D jtag router has core control registers that provide the same (or similar) functionality as the tap control register, for individual cores accessible through the same tap (e.g. through a DAP). Core control registers are located at address "0x60 + core-id" of the ROUTER address space (IR=ROUTER). It is sometimes helpful or even necessary to modify the core control register. This patch renames the "icepick_d_coreid" function to the more appropriate "icepick_d_core_control" and adds a "value" argument that allows writing of arbitrary value. "icepick_d_tapenable" is extended by an optional value argument so that core control can be written as the tap is enabled. Change-Id: I0e7f91b596cb5075364c6c233348508f58e0a901 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4141 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-02-14Add support for Cypress PSoC6 family of devicesBohdan Tymkiv1-0/+134
* Tested on CY8CKIT-001 kit with PSoC6 daughter board. * Tested with several J-Link adapters (Ultra+, Basic) Change-Id: I0a818c231e5f0b270c7774037b38d23221d59417 Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4233 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-02-14psoc4: update for 4x00BLE, L, M, S and PRoC BLE devicesTomas Vanek1-13/+76
Flash ROM API command PSOC4_CMD_SET_IMO48 is now optional on new devices. Also code tidy up: - improved system ROM call error detection - probe does not require the target to be halted - default_padded_value and erased_value set to 0 - fixed endianess problem in flash write and protection setting - removed fancy chip detection table as it would be updated too often - psoc4 flash_autoerase is now on by default to ease programming psoc4.cfg distinguishes chip family and uses either proprietary acquire function of a KitProg adapter or TEST_MODE workaround to "reset halt" Change-Id: I2c75ec46ed0a95e09274fad70b62d6eed7b9ecdf Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3807 Tested-by: jenkins Reviewed-by: David Girault <david.f.girault@gmail.com>
2018-02-02Merge branch 'master' into updateTim Newsome17-25/+266
Change-Id: I2cd34ed5bb1903736ae8ce109acebaf13bf49805
2018-02-01Kinetis_ke: add KEAx family to texi and cfg commentTomas Vanek1-1/+1
Change-Id: Id8f676b027f57fc540473c1a3a01bdd2ec49a200 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4232 Tested-by: jenkins Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
2018-01-30tcl: interface: harmonise RPi configsPaul Fertser3-12/+21
Make all configs specify same JTAG and SWD GPIO numbers. Change-Id: I65b09c1671c97f253f0aab88e511de7409d91e0a Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3932 Tested-by: jenkins
2018-01-25tcl: target: klx: use 1KiB for working areaPaul Fertser1-2/+2
Some parts have only that much. Reported by robertfoos_ on IRC. Change-Id: I684fdccfa62cf726466ddc467543a990fd88c4dc Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4369 Reviewed-by: Robert Foss <robert.foss@memcpy.io> Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-16target: add initial imx7.cfgOleksij Rempel1-0/+37
Change-Id: I899a215049ff0bc8840463c71018867ef71b5b90 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4190 Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkins
2018-01-13jtagspi: new protocol that includes transfer lengthRobert Jordens1-7/+1
This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13ftdi swd: disable SWD output pin during inputPatrick Stewart3-0/+117
* Disables the data output pin while SWD is reading, so that a simple FTDI SWD interface can be made by connecting TCK to SWD_CLK and TDI+TDO directly to SWDIO. Enabled by setting SWDIO_OE to 0. Change-Id: I7d3b71cf3f4eea163cb320aff69ed95d219190bd Signed-off-by: Patrick Stewart <patstew@gmail.com> Signed-off-by: Roger Lendenmann <roger.lendenmann@intel.com> Reviewed-on: http://openocd.zylin.com/2274 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2018-01-13digilent_jtag_smt2_nc: add supportRobert Jordens1-0/+18
The Digilent SMT2 NC is nominally the connector-less version of the SMT2. But neither the SMT2 configuration nor the HS3 configuration work for on the Xilinx KCU105 board where the SMT2 NC is used. Change-Id: Ieb27cbc6d8b0f9c64ef778e4e0c839acc85ec0ef Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4187 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13XCF (Xilinx platfrom flash) support.barthess2-0/+36
Change-Id: I4ee6db5f0abdb9fd279cc0edd13f71952a9d295d Signed-off-by: Uladzimir Pylinski <barthess@yandex.ru> Reviewed-on: http://openocd.zylin.com/3914 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13board: consolidate st_nucleo_l4 boardsPushpal Sidhu1-3/+2
We can now use the generic stlink.cfg which allows for both ST-LINK/V2 and V2-1 debuggers. Change-Id: I229c6fe5f6a6a4f2d3c787a49939846f102f9e24 Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com> Reviewed-on: http://openocd.zylin.com/4313 Tested-by: jenkins Reviewed-by: Karl Palsson <karlp@tweak.net.au> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-12Added config files for stm8l152 stm8s003 and stm8s105Ake Rehnman3-0/+31
Change-Id: I26cc401aafac01e5aed8eac605488da5221ffdc2 Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com> Reviewed-on: http://openocd.zylin.com/4268 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-12-29Remove board files that I shouldn't have addedTim Newsome3-96/+0
There are 3 other ones for the SiFive target. Change-Id: I987331a82186a3738096cc390c91889118bf9ac2
2017-12-29add configs for the SiFive boardsLiviu Ionescu3-0/+78
- the HiFive1 board definition includes the FTDI interface - the Arty boards require external interface definitions
2017-12-28Add config files for SiFive RISC-V hardware.Tim Newsome3-0/+96
Copied from https://github.com/gnu-mcu-eclipse/openocd Change-Id: Ia0b3e192ca8b3bae6035623d605c9980e9bccd2c
2017-12-22Merge branch 'master' into updateTim Newsome47-81/+729
Change-Id: Icec244b174cc0c67ab58961649a369db7f344824
2017-12-20config for ESPRESSObin from Globalscale Tech. Inc.Jiri Kastner1-0/+7
Change-Id: I77f536a9d2e901ebcef0a7dd0f205e5332b1d382 Signed-off-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/4303 Tested-by: jenkins Reviewed-by: Forest Crossman <cyrozap@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-12-20configs for Marvell Armada 3700Jiri Kastner3-0/+78
Change-Id: I367f39c9bc9e58380d6d5b500d5368d5173d96bd Signed-off-by: Jiri Kastner <cz172638@gmail.com> Signed-off-by: Forest Crossman <cyrozap@gmail.com> Reviewed-on: http://openocd.zylin.com/4302 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-12-12jtag: drivers: stlink: handle all versions with single configPaul Fertser26-63/+45
Extend HLA interface to allow multiple VID/PID pairs and use it to autodetect the connected stlink version. Change-Id: I35cd895b2260e23cf0e8fcb1fc11a78c2b99c69b Signed-off-by: Paul Fertser <fercerpav@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3961 Tested-by: jenkins Reviewed-by: Karl Palsson <karlp@tweak.net.au> Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-12-08config: stm32l01x and stm32l02x chips supportelmot1-2/+2
New low-end chips have only 2k of RAM, workarea size adjusted Change-Id: Ibfccd73fef9e6dabffc87d901736c5626ce411fe Signed-off-by: Ilia Motornyi <elijah.mot@gmail.com> Reviewed-on: http://openocd.zylin.com/4308 Tested-by: jenkins Reviewed-by: Karl Palsson <karlp@tweak.net.au> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2017-12-07stm8 : new targetAke Rehnman2-0/+171
New STM8 target based mostly on mips4k. Target communication through STLINK/SWIM. No flash driver yet but it is still possible to program flash through load_image command. The usual target debug methods are implemented. Change-Id: I7216f231d3ac7c70cae20f1cd8463c2ed864a329 Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com> Reviewed-on: http://openocd.zylin.com/3953 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-12-06Add STM32H7 config filesAlexandre Torgue4-0/+123
Add 2 target files: -stm32h7x.cfg -stm32h7x_dual_bank.cfg Add 2 config files for: -STM32H743zi-nucleo bord -STM32H743i and STM32H753i eval boards. Change-Id: I2aae2c5acff4f3ff8e1bf232fda5a11a87f71703 Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-on: http://openocd.zylin.com/4182 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2017-10-27tcl/interface/ftdi/openrd: Fix FTDI channel + device descriptionJonathan McDowell2-7/+4
Similar to the Sheevaplug fix inf95f8b70fbd0f7e9c91a2d9006b1abb2dd07ebf2 the OpenRD device has its JTAG interface on the first channel of the ft2232, which is 0 for the new driver but was 1 for the old one. Correct the config file appropriately. Also the device description was missing the trailing " B" and thus not picking up the device correctly. Finally add an adapter_khz setting in the OpenRD board configuration file - set to 2MHz to match the Sheeva variant. Confirmed as working thanks to Phil Hands providing me access to his hardware to test on. See also Debian Bug#793214; https://bugs.debian.org/793214 Change-Id: Ifacf53124eaa330bbbdf36dfa79e3256bf2a5201 Signed-off-by: Jonathan McDowell <noodles@earth.li> Reviewed-on: http://openocd.zylin.com/4254 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-10-26No RussianPalmer Dabbelt2-0/+0
2017-10-16tcl: add hi3798 target and Tocoding Poplar board configPeter Griffin2-0/+77
This config covers the 4x Cortex A53 CPUs. A custom connector is required from J14 to standard ARM JTAG on v1 boards. However v2 hardware should have a standard FTSH-105-01-L-DV connector. Pinmuxing code to enable JTAG pins is included in l-loader-poplar repository, so board is flashed with open source code, JTAG is available at very early boot. Alternatively the following pokes can be issued from U-Boot to enable JTAG (e.g. to debug hisilicon SDK). mw 0xf8a210ec 0x130; mw 0xf8a210f0 0x130; mw 0xf8a210f4 0x130; mw 0xf8a210f8 0x130; mw 0xf8a210fc 0x130; mw 0xf8a21100 0x130; Change-Id: I2b83dfcb3dc5461c1620f94dd99aa7b31fdda59b Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-on: http://openocd.zylin.com/4161 Tested-by: jenkins Reviewed-by: Jiri Kastner <cz172638@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-10-03nrf5: Add nRF52832-QFAA supportSlowcoder1-1/+14
Change-Id: Ica9e34e873cac182662b1e32a9b3164dbc0c935f Signed-off-by: Slowcoder <slowcoder@gmail.com> Reviewed-on: http://openocd.zylin.com/4210 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-10-03target: atheros_ar9344: add simple uart0 testOleksij Rempel1-0/+23
in some cases we need something to test if uart is actually properly connected. Change-Id: I5a16b053164b34bb30ae8370753be12887a85c51 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4194 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-10-03board: add TP-Link WDR4300 configOleksij Rempel1-0/+160
tested on TP-Link WDR4300 v1.7 Change-Id: If2b456afac835ab3a3987d434d20824c7ba75b93 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4192 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-10-03target: add atheros_ar9344.cfgOleksij Rempel1-0/+16
Change-Id: I005b4c78ccb0fec8d38a25430cb49c580dcd8df5 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4191 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-10-03board: tp-link_tl-mr3020: add ath79 supportOleksij Rempel1-0/+2
Finally we can use this driver by default! Change-Id: I09d215d1bd1dc16873a7379637e6869af65ad8f1 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4193 Tested-by: jenkins Reviewed-by: Dmytro <dioptimizer@hotmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2017-10-03tcl/interface/ftdi: improve minimodule configDiego Herranz1-7/+6
- Tested on a real FT2232H MiniModule, so warning removed. - Every pin initially set to high impedance except TCK, TDI, TDO and TMS: Safest values given it's an evaluation board and the rest of pins might be connected to something else. - Reset is now initially de-asserted (it was asserted which is not recommended). - nRST pin choice is arbitrary so comment added (wondering if it should be an "echo"). - "-oe" option added to NRST signal so it can be set as high impedance (tri-stated). Change-Id: I967ab0c7bbccf72dbf6d6d78b3180b74e016e0d6 Signed-off-by: Diego Herranz <diegoherranz@diegoherranz.com> Reviewed-on: http://openocd.zylin.com/4185 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
generated by cgit v1.1 at 2025-09-20 20:46:11 +0000