Merge branch 'master' into from_upstream

Conflicts:
	src/rtos/rtos.c
	src/rtos/rtos.h
	src/server/gdb_server.c

Change-Id: Icd5a8165fe111f699542530c9cb034faf30e09b2

83 files changed, 1030 insertions, 170 deletions

diff --git a/tcl/board/avnet_ultrazed-eg.cfg b/tcl/board/avnet_ultrazed-eg.cfg
new file mode 100644
index 0000000..a0ac5c6
--- /dev/null
+++ b/tcl/board/avnet_ultrazed-eg.cfg
@@ -0,0 +1,16 @@
+#
+# AVNET UltraZED EG StarterKit
+# UlraScale-EG plus IO Carrier with on-board digilent smt2
+#
+source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
+# jtag transport only
+transport select jtag
+# reset lines are not wired
+reset_config none
+
+# slow default clock
+adapter_khz 1000
+
+set CHIPNAME uscale
+
+source [find target/xilinx_ultrascale.cfg]
diff --git a/tcl/board/kasli.cfg b/tcl/board/kasli.cfg
new file mode 100644
index 0000000..2c5e268
--- /dev/null
+++ b/tcl/board/kasli.cfg
@@ -0,0 +1,15 @@
+interface ftdi
+ftdi_device_desc "Quad RS232-HS"
+ftdi_vid_pid 0x0403 0x6011
+ftdi_channel 0
+ftdi_layout_init 0x0008 0x000b
+# ftdi_location 1:8
+
+reset_config none
+transport select jtag
+adapter_khz 25000
+
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
+source [find fpga/xilinx-xadc.cfg]
+source [find fpga/xilinx-dna.cfg]
diff --git a/tcl/board/kc705.cfg b/tcl/board/kc705.cfg
index 39f7fa3..e032e9b 100644
--- a/tcl/board/kc705.cfg
+++ b/tcl/board/kc705.cfg
@@ -3,6 +3,8 @@
 source [find interface/ftdi/digilent-hs1.cfg]
 source [find cpld/xilinx-xc7.cfg]
 source [find cpld/jtagspi.cfg]
+source [find fpga/xilinx-xadc.cfg]
+source [find fpga/xilinx-dna.cfg]
 adapter_khz 25000
 
 # example command to write bitstream, soft-cpu bios and runtime:
diff --git a/tcl/board/kcu105.cfg b/tcl/board/kcu105.cfg
new file mode 100644
index 0000000..c8daea6
--- /dev/null
+++ b/tcl/board/kcu105.cfg
@@ -0,0 +1,11 @@
+# xilinx ultrascale
+# http://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
+
+source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
+
+set CHIP XCKU040
+source [find cpld/xilinx-xcu.cfg]
+
+source [find cpld/jtagspi.cfg]
+
+adapter_khz 25000
diff --git a/tcl/board/sayma_amc.cfg b/tcl/board/sayma_amc.cfg
new file mode 100644
index 0000000..5d338ed
--- /dev/null
+++ b/tcl/board/sayma_amc.cfg
@@ -0,0 +1,45 @@
+# Sayma AMC is an FPGA board for the µTCA AMC format
+# The board is open hardware (CERN OHL) and the gateware and software
+# running on it are open source (ARTIQ, LGPLv3+).
+#
+# https://github.com/m-labs/sinara/wiki/Sayma
+#
+# It contains a Xilinx Kintex Ultrascale 040 FPGA (xcku040).
+# There is a SCANSTA112SM JTAG router on the board which is configured to
+# automatically add devices to the JTAG svcan chain when they are added.
+# Sayma AMC is usually combined with Sayma RTM (rear transition module)
+# which features an Artix 7 FPGA.
+
+interface ftdi
+ftdi_device_desc "Quad RS232-HS"
+ftdi_vid_pid 0x0403 0x6011
+ftdi_channel 0
+# Use this to distinguish multiple boards by topology
+#ftdi_location 5:1
+# sampling on falling edge generally seems to work and accelerates things but
+# is not fully tested
+#ftdi_tdo_sample_edge falling
+# EN_USB_JTAG on ADBUS7: out, high
+# USB_nTRST on ADBUS4: out, high, but R46 is DNP
+ftdi_layout_init 0x0098 0x008b
+#ftdi_layout_signal EN_USB -data 0x0080
+#ftdi_layout_signal nTRST -data 0x0010
+reset_config none
+
+adapter_khz 5000
+
+transport select jtag
+
+# Add the RTM Artix to the chain. Note that this changes the PLD numbering.
+# Unfortunately openocd TAPs can't be disabled after they have been added and
+# before `init`.
+#source [find cpld/xilinx-xc7.cfg]
+
+set CHIP XCKU040
+source [find cpld/xilinx-xcu.cfg]
+
+set XILINX_USER1 0x02
+set XILINX_USER2 0x03
+set JTAGSPI_IR $XILINX_USER1
+source [find cpld/jtagspi.cfg]
+flash bank xcu.spi1 jtagspi 0 0 0 0 xcu.proxy $XILINX_USER2
diff --git a/tcl/board/steval-idb007v1.cfg b/tcl/board/steval-idb007v1.cfg
new file mode 100644
index 0000000..24dbd1e
--- /dev/null
+++ b/tcl/board/steval-idb007v1.cfg
@@ -0,0 +1,4 @@
+# This is an evaluation board with a single BlueNRG-1 chip.
+# http://www.st.com/content/st_com/en/products/evaluation-tools/solution-evaluation-tools/communication-and-connectivity-solution-eval-boards/steval-idb008v1.html
+set CHIPNAME bluenrg-1
+source [find target/bluenrg-x.cfg]
diff --git a/tcl/board/steval-idb008v1.cfg b/tcl/board/steval-idb008v1.cfg
new file mode 100644
index 0000000..3e9d0e5
--- /dev/null
+++ b/tcl/board/steval-idb008v1.cfg
@@ -0,0 +1,4 @@
+# This is an evaluation board with a single BlueNRG-2 chip.
+# http://www.st.com/content/st_com/en/products/evaluation-tools/solution-evaluation-tools/communication-and-connectivity-solution-eval-boards/steval-idb007v1.html
+set CHIPNAME bluenrg-2
+source [find target/bluenrg-x.cfg]
diff --git a/tcl/cpld/xilinx-xcu.cfg b/tcl/cpld/xilinx-xcu.cfg
new file mode 100644
index 0000000..3270597
--- /dev/null
+++ b/tcl/cpld/xilinx-xcu.cfg
@@ -0,0 +1,72 @@
+# Xilinx Ultrascale (Kintex, Virtex, Zynq)
+# https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME xcu
+}
+
+# The cvarious chips in the Ultrascale family have different IR length.
+# Set $CHIP before including this file to determine the device.
+array set _XCU_DATA {
+	XCKU025 {0x03824093 6}
+	XCKU035 {0x03823093 6}
+	XCKU040 {0x03822093 6}
+	XCKU060 {0x03919093 6}
+	XCKU095 {0x03844093 6}
+	XCKU3P {0x04A63093 6}
+	XCKU5P {0x04A62093 6}
+	XCKU9P {0x0484A093 6}
+	XCKU11P {0x04A4E093 6}
+	XCKU13P {0x04A52093 6}
+	XCKU15P {0x04A56093 6}
+	XCVU065 {0x03939093 6}
+	XCVU080 {0x03843093 6}
+	XCVU095 {0x03842093 6}
+	XCVU3P {0x04B39093 6}
+	XCKU085 {0x0380F093 12}
+	XCKU115 {0x0390D093 12}
+	XCVU125 {0x0392D093 12}
+	XCVU5P {0x04B2B093 12}
+	XCVU7P {0x04B29093 12}
+	XCVU160 {0x03933093 18}
+	XCVU190 {0x03931093 18}
+	XCVU440 {0x0396D093 18}
+	XCVU9P {0x04B31093 18}
+	XCVU11P {0x04B49093 18}
+	XCVU13P {0x04B51093 24}
+}
+
+if { ![info exists CHIP] } {
+	error "set CHIP to one of "[concat [array names _XCU_DATA]]
+}
+
+if { ![llength [array names _XCU_DATA $CHIP]] } {
+	error "unknown CHIP: "$CHIP
+}
+
+set _EXPID [lindex $_XCU_DATA($CHIP) 0]
+set _IRLEN [lindex $_XCU_DATA($CHIP) 1]
+
+# the 4 top bits (28:31) are the die stepping/revisions. ignore it.
+jtag newtap $_CHIPNAME tap -irlen $_IRLEN -ignore-version -expected-id $_EXPID
+
+pld device virtex2 $_CHIPNAME.tap 1
+
+set XCU_JSHUTDOWN 0x0d
+set XCU_JPROGRAM 0x0b
+set XCU_JSTART 0x0c
+set XCU_BYPASS 0x3f
+
+proc xcu_program {tap} {
+	global XCU_JSHUTDOWN XCU_JPROGRAM XCU_JSTART XCU_BYPASS
+	irscan $tap $XCU_JSHUTDOWN
+	irscan $tap $XCU_JPROGRAM
+	runtest 60000
+	#JSTART prevents this from working...
+	#irscan $tap $XCU_JSTART
+	runtest 2000
+	irscan $tap $XCU_BYPASS
+	runtest 2000
+}
diff --git a/tcl/fpga/xilinx-dna.cfg b/tcl/fpga/xilinx-dna.cfg
new file mode 100644
index 0000000..a1d5ba3
--- /dev/null
+++ b/tcl/fpga/xilinx-dna.cfg
@@ -0,0 +1,43 @@
+proc xilinx_dna_addr {chip} {
+	array set addrs {
+		Spartan6 0x30
+		Series7 0x17
+	}
+	return $addrs($chip)
+}
+
+# Get the "Device DNA".
+# Most Xilinx FPGA devices contain an embedded, unique device identifier.
+# The identifier is nonvolatile, permanently programmed into
+# the FPGA, and is unchangeable providing a great serial / tracking number.
+# This function returns the DNA as a 64 bit integer with the 7 LSBs zeroed.
+# This is compatible with the FUSE DNA which contains all 64 bits.
+proc xilinx_get_dna {tap chip} {
+	set XC7_ISC_ENABLE 0x10
+	set XC7_ISC_DISABLE 0x16
+	set XC7_ISC_DNA [xilinx_dna_addr $chip]
+
+	irscan $tap $XC7_ISC_ENABLE
+	runtest 64
+	irscan $tap $XC7_ISC_DNA
+	scan [drscan $tap 32 0 32 0] "%08x %08x" hi lo
+	runtest 64
+	irscan $tap $XC7_ISC_DISABLE
+	runtest 64
+	# openocd interprets DR scans as LSB first, bit-reverse it
+	return [scan [string reverse [format "%032b%032bb0" $lo $hi]] "%i"]
+}
+
+# Print out the "Device DNA" in the same format that impact uses.
+proc xilinx_print_dna {dna} {
+	set dna [expr $dna >> 64 - 57]
+	echo [format "DNA = %057b (0x%016x)" $dna $dna]
+}
+
+proc xc7_get_dna {tap} {
+	return [xilinx_get_dna $tap Series7]
+}
+
+proc xc6s_get_dna {tap} {
+	return [xilinx_get_dna $tap Spartan6]
+}
diff --git a/tcl/fpga/xilinx-xadc.cfg b/tcl/fpga/xilinx-xadc.cfg
new file mode 100644
index 0000000..3869104
--- /dev/null
+++ b/tcl/fpga/xilinx-xadc.cfg
@@ -0,0 +1,159 @@
+# Xilinx XADC support for 7 Series FPGAs
+#
+# The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die
+# temperature, internal power supply rail voltages as well as external
+# voltages. The XADC is available both from fabric as well as through the
+# JTAG TAP.
+#
+# This code implements access throught the JTAG TAP.
+#
+# https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
+
+# build a 32 bit DRP command for the XADC DR
+proc xadc_cmd {cmd addr data} {
+	array set cmds {
+		NOP 0x00
+		READ 0x01
+		WRITE 0x02
+	}
+	return [expr ($cmds($cmd) << 26) | ($addr << 16) | ($data << 0)]
+}
+
+# XADC register addresses
+# Some addresses (status registers 0-3) have special function when written to.
+proc XADC {key} {
+	array set addrs {
+		TEMP 0x00
+		LOCK 0x00
+		VCCINT 0x01
+		VCCAUX 0x02
+		VAUXEN 0x02
+		VPVN 0x03
+		RESET 0x03
+		VREFP 0x04
+		VREFN 0x05
+		VCCBRAM 0x06
+		SUPAOFFS 0x08
+		ADCAOFFS 0x09
+		ADCAGAIN 0x0a
+		VCCPINT 0x0d
+		VCCPAUX 0x0e
+		VCCODDR 0x0f
+		VAUX0 0x10
+		VAUX1 0x11
+		VAUX2 0x12
+		VAUX3 0x13
+		VAUX4 0x14
+		VAUX5 0x15
+		VAUX6 0x16
+		VAUX7 0x17
+		VAUX8 0x18
+		VAUX9 0x19
+		VAUX10 0x1a
+		VAUX11 0x1b
+		VAUX12 0x1c
+		VAUX13 0x1d
+		VAUX14 0x1e
+		VAUX15 0x1f
+		SUPBOFFS 0x30
+		ADCBOFFS 0x31
+		ADCBGAIN 0x32
+		FLAG 0x3f
+		CFG0 0x40
+		CFG1 0x41
+		CFG2 0x42
+		SEQ0 0x48
+		SEQ1 0x49
+		SEQ2 0x4a
+		SEQ3 0x4b
+		SEQ4 0x4c
+		SEQ5 0x4d
+		SEQ6 0x4e
+		SEQ7 0x4f
+		ALARM0 0x50
+		ALARM1 0x51
+		ALARM2 0x52
+		ALARM3 0x53
+		ALARM4 0x54
+		ALARM5 0x55
+		ALARM6 0x56
+		ALARM7 0x57
+		ALARM8 0x58
+		ALARM9 0x59
+		ALARM10 0x5a
+		ALARM11 0x5b
+		ALARM12 0x5c
+		ALARM13 0x5d
+		ALARM14 0x5e
+		ALARM15 0x5f
+	}
+	return $addrs($key)
+}
+
+# Select the XADC DR
+proc xadc_select {tap} {
+	set XADC_IR 0x37
+	irscan $tap $XADC_IR
+	runtest 10
+}
+
+# XADC transfer
+proc xadc_xfer {tap cmd addr data} {
+	set ret [drscan $tap 32 [xadc_cmd $cmd $addr $data]]
+	runtest 10
+	return [expr 0x$ret]
+}
+
+# XADC register write
+proc xadc_write {tap addr data} {
+	xadc_xfer $tap WRITE $addr $data
+}
+
+# XADC register read, non-pipelined
+proc xadc_read {tap addr} {
+	xadc_xfer $tap READ $addr 0
+	return [xadc_xfer $tap NOP 0 0]
+}
+
+# convert 16 bit register code from ADC measurement on
+# external voltages (VAUX) to Volt
+proc xadc_volt {code} {
+	return [expr $code * 1./(1 << 16)]
+}
+
+# convert 16 bit temperature measurement to Celsius
+proc xadc_temp {code} {
+	return [expr $code * 503.975/(1 << 16) - 273.15]
+}
+
+# convert 16 bit suppply voltage measurement to Volt
+proc xadc_sup {code} {
+	return [expr $code * 3./(1 << 16)]
+}
+
+# perform a single channel measurement using default settings
+proc xadc_single {tap ch} {
+	set cfg0 [xadc_read $tap [XADC CFG0]]
+	set cfg1 [xadc_read $tap [XADC CFG1]]
+	# set channel
+	xadc_write $tap [XADC CFG0] $cfg0
+	# single channel, disable the sequencer
+	xadc_write $tap [XADC CFG1] 0x3000
+	# leave some time for the conversion
+	runtest 100
+	set ret [xadc_read $tap [XADC $ch]]
+	# restore CFG0/1
+	xadc_write $tap [XADC CFG0] $cfg0
+	xadc_write $tap [XADC CFG1] $cfg1
+	return $ret
+}
+
+# measure all internal voltages
+proc xadc_report {tap} {
+	xadc_select $tap
+	echo "TEMP [format %.2f [xadc_temp [xadc_single $tap TEMP]]] C"
+	foreach ch [list VCCINT VCCAUX VCCBRAM VPVN VREFP VREFN \
+		VCCPINT VCCPAUX VCCODDR] {
+		echo "$ch [format %.3f [xadc_sup [xadc_single $tap $ch]]] V"
+	}
+}
diff --git a/tcl/interface/altera-usb-blaster.cfg b/tcl/interface/altera-usb-blaster.cfg
index f19abfe..1bfef9d 100644
--- a/tcl/interface/altera-usb-blaster.cfg
+++ b/tcl/interface/altera-usb-blaster.cfg
@@ -5,6 +5,7 @@
 #
 
 interface usb_blaster
+usb_blaster_lowlevel_driver ftdi
 # These are already the defaults.
 # usb_blaster_vid_pid 0x09FB 0x6001
 # usb_blaster_device_desc "USB-Blaster"
diff --git a/tcl/interface/buspirate.cfg b/tcl/interface/buspirate.cfg
index 2b68538..c2f3a83 100644
--- a/tcl/interface/buspirate.cfg
+++ b/tcl/interface/buspirate.cfg
@@ -15,7 +15,7 @@ buspirate_speed normal ;# or fast
 # voltage regulator Enabled = 1 Disabled = 0
 #buspirate_vreg 0
 
-# pin mode normal or open-drain
+# pin mode normal or open-drain (jtag only)
 #buspirate_mode normal
 
 # pullup state Enabled = 1 Disabled = 0
diff --git a/tcl/interface/ft232r.cfg b/tcl/interface/ft232r.cfg
new file mode 100644
index 0000000..b4f71c8
--- /dev/null
+++ b/tcl/interface/ft232r.cfg
@@ -0,0 +1,2 @@
+interface ft232r
+adapter_khz 1000
diff --git a/tcl/interface/ftdi/pipistrello.cfg b/tcl/interface/ftdi/pipistrello.cfg
index b51405a..5ee5be5 100644
--- a/tcl/interface/ftdi/pipistrello.cfg
+++ b/tcl/interface/ftdi/pipistrello.cfg
@@ -10,4 +10,4 @@ ftdi_layout_init 0x0008 0x000b
 reset_config none
 # this generally works fast: the fpga can handle 30MHz, the spi flash can handle
 # 54MHz with simple read, no dummy cycles, and wait-for-write-completion
-adapter_khz 30000
+adapter_khz 10000
diff --git a/tcl/target/1986Be1T.cfg b/tcl/target/1986Be1T.cfg
index 7b0c35f..ecb3f8a 100644
--- a/tcl/target/1986Be1T.cfg
+++ b/tcl/target/1986Be1T.cfg
@@ -34,9 +34,10 @@ if { [info exists CPUTAPID] } {
    }
 }
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 # use AHB-Lite SRAM for work area
 $_TARGETNAME configure -work-area-phys 0x20100000 -work-area-size $_WORKAREASIZE -work-area-backup 0
diff --git a/tcl/target/adsp-sc58x.cfg b/tcl/target/adsp-sc58x.cfg
index 369137e..e2b6952 100644
--- a/tcl/target/adsp-sc58x.cfg
+++ b/tcl/target/adsp-sc58x.cfg
@@ -27,9 +27,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_a -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -event examine-end {
    global _TARGETNAME
diff --git a/tcl/target/aducm360.cfg b/tcl/target/aducm360.cfg
index 785c18c..ca4bc68 100755
--- a/tcl/target/aducm360.cfg
+++ b/tcl/target/aducm360.cfg
@@ -32,7 +32,8 @@ if { [info exists CPUTAPID] } {
    set _CPUTAPID 0x2ba01477
 }
 
-swd newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 # SWD/JTAG speed
 adapter_khz 1000
@@ -41,7 +42,7 @@ adapter_khz 1000
 ## Target configuration
 ##
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 # allocate the working area
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
diff --git a/tcl/target/altera_fpgasoc.cfg b/tcl/target/altera_fpgasoc.cfg
index 25fe1f4..1fbc5a3 100644
--- a/tcl/target/altera_fpgasoc.cfg
+++ b/tcl/target/altera_fpgasoc.cfg
@@ -14,7 +14,7 @@ if { [info exists DAP_TAPID] } {
         set _DAP_TAPID 0x4ba00477
 }
 
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
         -expected-id $_DAP_TAPID
 
 # Subsidiary TAP: fpga
@@ -42,7 +42,8 @@ set _TARGETNAME1 $_CHIPNAME.cpu.0
 set _TARGETNAME2 $_CHIPNAME.cpu.1
 
 # A9 core 0
-target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \
         -coreid 0 -dbgbase 0x80110000
 
 $_TARGETNAME1 configure -event reset-start { adapter_khz 1000 }
@@ -51,7 +52,7 @@ $_TARGETNAME1 configure -event gdb-attach { halt }
 
 
 # A9 core 1
-#target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \
+#target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \
 #        -coreid 1 -dbgbase 0x80112000
 
 #$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }
diff --git a/tcl/target/am335x.cfg b/tcl/target/am335x.cfg
index 3ca196b..02d8c7e 100644
--- a/tcl/target/am335x.cfg
+++ b/tcl/target/am335x.cfg
@@ -12,7 +12,7 @@ if { [info exists CHIPNAME] } {
 if { [info exists DEFAULT_TAPS] } {
 	set _DEFAULT_TAPS "$DEFAULT_TAPS"
 } else {
-	set _DEFAULT_TAPS "$_CHIPNAME.dap"
+	set _DEFAULT_TAPS "$_CHIPNAME.tap"
 }
 
 #
@@ -23,8 +23,9 @@ if { [info exists DAP_TAPID] } {
 } else {
 	set _DAP_TAPID 0x4b6b902f
 }
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0"
+jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0"
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
 
 #
 # M3 DAP
@@ -34,8 +35,9 @@ if { [info exists M3_DAP_TAPID] } {
 } else {
 	set _M3_DAP_TAPID 0x4b6b902f
 }
-jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0"
+jtag newtap $_CHIPNAME m3_tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
+jtag configure $_CHIPNAME.m3_tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0"
+dap create $_CHIPNAME.m3_dap -chain-position $_CHIPNAME.m3_tap
 
 #
 # ICEpick-D (JTAG route controller)
@@ -66,13 +68,13 @@ proc enable_default_taps { taps } {
 # Cortex-M3 target
 #
 set _TARGETNAME_2 $_CHIPNAME.m3
-target create $_TARGETNAME_2 cortex_m -chain-position $_CHIPNAME.m3_dap
+target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.m3_dap
 
 #
 # Cortex-A8 target
 #
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80001000
 
 # SRAM: 64K at 0x4030.0000; use the first 16K
 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
diff --git a/tcl/target/am437x.cfg b/tcl/target/am437x.cfg
index fe0ffff..8ce0941 100644
--- a/tcl/target/am437x.cfg
+++ b/tcl/target/am437x.cfg
@@ -458,6 +458,7 @@ if { [info exists M3_DAP_TAPID] } {
 }
 jtag newtap $_CHIPNAME $M3_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
 jtag configure $M3_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 11 0"
+dap create $M3_NAME.dap -chain-position $M3_NAME
 
 #
 # DebugSS DAP
@@ -469,6 +470,7 @@ if { [info exists DAP_TAPID] } {
 }
 jtag newtap $_CHIPNAME $DEBUGSS_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
 jtag configure $DEBUGSS_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 12 0"
+dap create $DEBUGSS_NAME.dap -chain-position $DEBUGSS_NAME
 
 #
 # ICEpick-D (JTAG route controller)
@@ -486,7 +488,7 @@ jtag configure $JRC_NAME -event post-reset "runtest 100"
 #
 # Cortex-A9 target
 #
-target create $_TARGETNAME cortex_a -chain-position $DEBUGSS_NAME -coreid 0 -dbgbase 0x80000000
+target create $_TARGETNAME cortex_a -dap $DEBUGSS_NAME.dap -coreid 0 -dbgbase 0x80000000
 
 
 # SRAM: 256K at 0x4030.0000
diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg
index c00dae9..5c4e315 100644
--- a/tcl/target/amdm37x.cfg
+++ b/tcl/target/amdm37x.cfg
@@ -86,8 +86,8 @@ source [find target/icepick.cfg]
 
 # Secondary TAP: DAP is closest to the TDO output
 # The TAP enable event also needs to be described
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
    "icepick_c_tapenable $_CHIPNAME.jrc 3"
 
 # These taps are only present in the DM37x series.
@@ -141,7 +141,8 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
 
 # Create the CPU target to be used with GDB:  Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
 
 # The DM37x has 64K of SRAM starting at address 0x4020_0000.  Allow the first
 # 16K to be used as a scratchpad for OpenOCD.
diff --git a/tcl/target/armada370.cfg b/tcl/target/armada370.cfg
index 40c779b..5b84637 100644
--- a/tcl/target/armada370.cfg
+++ b/tcl/target/armada370.cfg
@@ -16,10 +16,11 @@ if { [info exists CPUTAPID] } {
    set _CPUTAPID 0x4ba00477
 }
 
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
 
 proc armada370_dbginit {target} {
      cortex_a dbginit
diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg
index fca655d..e7dec4b 100644
--- a/tcl/target/at91sam3XXX.cfg
+++ b/tcl/target/at91sam3XXX.cfg
@@ -55,9 +55,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 # 16K is plenty, the smallest chip has this much
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
diff --git a/tcl/target/at91sam3nXX.cfg b/tcl/target/at91sam3nXX.cfg
index 19bd33a..3450c26 100644
--- a/tcl/target/at91sam3nXX.cfg
+++ b/tcl/target/at91sam3nXX.cfg
@@ -18,9 +18,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME
diff --git a/tcl/target/at91sam4XXX.cfg b/tcl/target/at91sam4XXX.cfg
index ca80143..ff73670 100644
--- a/tcl/target/at91sam4XXX.cfg
+++ b/tcl/target/at91sam4XXX.cfg
@@ -35,9 +35,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 # 16K is plenty, the smallest chip has this much
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
diff --git a/tcl/target/at91samdXX.cfg b/tcl/target/at91samdXX.cfg
index 93a95c8..f0644d1 100644
--- a/tcl/target/at91samdXX.cfg
+++ b/tcl/target/at91samdXX.cfg
@@ -34,9 +34,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/atsamv.cfg b/tcl/target/atsamv.cfg
index b6c4842..d1f8454 100644
--- a/tcl/target/atsamv.cfg
+++ b/tcl/target/atsamv.cfg
@@ -32,9 +32,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/bcm281xx.cfg b/tcl/target/bcm281xx.cfg
index 224af79..6432a20 100644
--- a/tcl/target/bcm281xx.cfg
+++ b/tcl/target/bcm281xx.cfg
@@ -14,15 +14,17 @@ if { [info exists DAP_TAPID] } {
 	set _DAP_TAPID 0x4ba00477
 }
 
-jtag newtap $_CHIPNAME dap -expected-id $_DAP_TAPID -irlen 4
+jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4
 
 
 # Dual Cortex-A9
 set _TARGETNAME0 $_CHIPNAME.cpu0
 set _TARGETNAME1 $_CHIPNAME.cpu1
 
-target create $_TARGETNAME0 cortex_a -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x3fe10000
-target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap -coreid 1 -dbgbase 0x3fe12000
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME0 cortex_a -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x3fe10000
+target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0x3fe12000
 target smp $_TARGETNAME0 $_TARGETNAME1
 
 $_TARGETNAME0 configure -event gdb-attach {
diff --git a/tcl/target/bluenrg-x.cfg b/tcl/target/bluenrg-x.cfg
new file mode 100644
index 0000000..b0dd61a
--- /dev/null
+++ b/tcl/target/bluenrg-x.cfg
@@ -0,0 +1,74 @@
+#
+# bluenrg-1/2 devices support only SWD transports.
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME bluenrg-1
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 24kB-256bytes
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x5F00
+}
+
+adapter_khz 4000
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0bb11477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+set WDOG_VALUE 0
+set WDOG_VALUE_SET 0
+
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000100 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
+
+# In BlueNRG-X reset pin is actually a shutdown (power-off), so define reset as none
+reset_config none
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event halted {
+	global WDOG_VALUE
+	global WDOG_VALUE_SET
+	# Stop watchdog during halt, if enabled
+	mem2array value 32 0x40700008 1
+	set WDOG_VALUE [expr ($value(0))]
+	if [expr ($value(0) & (1 << 1))] {
+		set WDOG_VALUE_SET 1
+		mww 0x40700008 [expr ($value(0) & 0xFFFFFFFD)]
+	}
+}
+$_TARGETNAME configure -event resumed {
+	global WDOG_VALUE
+	global WDOG_VALUE_SET
+	if [expr $WDOG_VALUE_SET] {
+		# Restore watchdog enable value after resume
+		mww 0x40700008 $WDOG_VALUE
+		set WDOG_VALUE_SET 0
+       }
+}
diff --git a/tcl/target/cc26xx.cfg b/tcl/target/cc26xx.cfg
index 1492e6a..c3ac847 100755
--- a/tcl/target/cc26xx.cfg
+++ b/tcl/target/cc26xx.cfg
@@ -19,8 +19,8 @@ if { [info exists DAP_TAPID] } {
 } else {
    set _DAP_TAPID 0x4BA00477
 }
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
 
 #
 # ICEpick-C (JTAG route controller)
@@ -33,11 +33,12 @@ if { [info exists JRC_TAPID] } {
 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
 # A start sequence is needed to change from cJTAG (Compact JTAG) to
 # 4-pin JTAG before talking via JTAG commands
-jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
 jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
 
 #
 # Cortex-M3 target
 #
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
diff --git a/tcl/target/cc32xx.cfg b/tcl/target/cc32xx.cfg
index 154bf91..dfc4c17 100755
--- a/tcl/target/cc32xx.cfg
+++ b/tcl/target/cc32xx.cfg
@@ -26,10 +26,10 @@ if { [info exists DAP_TAPID] } {
 }
 
 if {[using_jtag]} {
-   jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
-   jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
+   jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+   jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
 } else {
-   swj_newdap $_CHIPNAME dap -expected-id $_DAP_TAPID
+   swj_newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID
 }
 
 #
@@ -50,4 +50,5 @@ if {[using_jtag]} {
 # Cortex-M3 target
 #
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
diff --git a/tcl/target/efm32.cfg b/tcl/target/efm32.cfg
index 33610d5..e22ce5c 100644
--- a/tcl/target/efm32.cfg
+++ b/tcl/target/efm32.cfg
@@ -1,5 +1,8 @@
 #
-# efm32 target
+# Silicon Labs (formerly Energy Micro) EFM32 target
+#
+# Note: All EFM32 chips have SWD support, but only newer series 1
+# chips have JTAG support.
 #
 
 source [find target/swj-dp.tcl]
@@ -21,15 +24,20 @@ if { [info exists WORKAREASIZE] } {
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-   set _CPUTAPID 0x2ba01477
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
 }
 
-swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 adapter_khz 1000
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/em357.cfg b/tcl/target/em357.cfg
index 24ffb04..5720071 100644
--- a/tcl/target/em357.cfg
+++ b/tcl/target/em357.cfg
@@ -50,12 +50,13 @@ if { [info exists FLASHSIZE] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 if { [using_jtag] } {
     swj_newdap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/exynos5250.cfg b/tcl/target/exynos5250.cfg
index 3678341..d3aaa98 100644
--- a/tcl/target/exynos5250.cfg
+++ b/tcl/target/exynos5250.cfg
@@ -17,7 +17,8 @@ if { [info exists CPUTAPID] } {
 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create ${_TARGETNAME}0 cortex_a -chain-position $_TARGETNAME
-target create ${_TARGETNAME}1 cortex_a -chain-position $_TARGETNAME
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap
+target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap
 
 target smp ${_TARGETNAME}0 ${_TARGETNAME}1
diff --git a/tcl/target/fm3.cfg b/tcl/target/fm3.cfg
index 78bbc94..a0610ce 100644
--- a/tcl/target/fm3.cfg
+++ b/tcl/target/fm3.cfg
@@ -31,9 +31,10 @@ if {[using_jtag]} {
 reset_config trst_only
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 # MB9BF506 has 64kB of SRAM on its main system bus 
 $_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
diff --git a/tcl/target/fm4.cfg b/tcl/target/fm4.cfg
index e5d0f8d..b79634d 100644
--- a/tcl/target/fm4.cfg
+++ b/tcl/target/fm4.cfg
@@ -19,9 +19,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
 
 adapter_khz 500
 
diff --git a/tcl/target/hi3798.cfg b/tcl/target/hi3798.cfg
index 9eda150..aa811d4 100644
--- a/tcl/target/hi3798.cfg
+++ b/tcl/target/hi3798.cfg
@@ -16,8 +16,8 @@ if { [info exists DAP_TAPID] } {
 }
 
 # declare the one JTAG tap to access the DAP
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
-
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 # declare the 4 main application cores
 set _TARGETNAME $_CHIPNAME.cpu
 set _smp_command ""
@@ -30,8 +30,10 @@ set $_TARGETNAME.cti(3) 0x80320000
 set _cores 4
 for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
 
+    cti create cti$_core -dap $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)] -ap-num 0
+
     set _command "target create ${_TARGETNAME}$_core aarch64 \
-                         -chain-position $_CHIPNAME.dap -coreid $_core -ctibase [set $_TARGETNAME.cti($_core)]"
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"
 
     if { $_core != 0 } {
         # non-boot core examination may fail
diff --git a/tcl/target/hi6220.cfg b/tcl/target/hi6220.cfg
index 7daa3c1..c2feb0b 100644
--- a/tcl/target/hi6220.cfg
+++ b/tcl/target/hi6220.cfg
@@ -16,7 +16,10 @@ if { [info exists DAP_TAPID] } {
 }
 
 # declare the one JTAG tap to access the DAP
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
+jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version
+
+# create the DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
 
 # declare the 8 main application cores
 set _TARGETNAME $_CHIPNAME.cpu
@@ -34,8 +37,10 @@ set $_TARGETNAME.cti(7) 0x801DB000
 set _cores 8
 for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
 
+    cti create cti$_core -dap $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)] -ap-num 0
+
     set _command "target create ${_TARGETNAME}$_core aarch64 \
-                         -chain-position $_CHIPNAME.dap -coreid $_core -ctibase [set $_TARGETNAME.cti($_core)]"
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"
 
     if { $_core != 0 } {
         # non-boot core examination may fail
@@ -52,5 +57,10 @@ for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
 
 eval $_smp_command
 
+cti create cti.sys -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0x80003000
+
 # declare the auxiliary Cortex-M3 core on AP #2 (runs mcuimage.bin)
-target create ${_TARGETNAME}.m3 cortex_m -chain-position $_CHIPNAME.dap -ap-num 2 -defer-examine
+target create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+
+# declare the auxiliary Cortex-A7 core
+target create ${_TARGETNAME}.a7 cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80210000 -defer-examine
diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg
index abd7b6a..0f160bb 100644
--- a/tcl/target/icepick.cfg
+++ b/tcl/target/icepick.cfg
@@ -63,7 +63,8 @@ proc icepick_c_router {jrc rw block register payload} {
 	irscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE
 
 	# ROUTER instructions are 32 bits wide
-	set old_dr_value [drscan $jrc 32 $new_dr_value -endstate DRPAUSE]
+	set old_dr_value 0x[drscan $jrc 32 $new_dr_value -endstate DRPAUSE]
+#	echo "\tOld router value:\t0x[format %x $old_dr_value]"
 }
 
 # Configure the icepick control register
@@ -109,15 +110,15 @@ proc icepick_c_tapenable {jrc port} {
 
 # jrc	== TAP name for the ICEpick
 # coreid== core id number 0..15 (not same as port number!)
-proc icepick_d_set_coreid {jrc coreid } {
-	icepick_c_router $jrc 1 0x6 $coreid 0x2008
+proc icepick_d_set_core_control {jrc coreid value } {
+	icepick_c_router $jrc 1 0x6 $coreid $value
 }
 
 # jrc	== TAP name for the ICEpick
 # port	== a port number, 0..15
 # Follow the sequence described in
 # http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf
-proc icepick_d_tapenable {jrc port coreid} {
+proc icepick_d_tapenable {jrc port coreid { value 0x2008 } } {
 	# First CONNECT to the ICEPick
 	icepick_c_connect $jrc
 	icepick_c_setup $jrc
@@ -125,8 +126,8 @@ proc icepick_d_tapenable {jrc port coreid} {
 	# Select the port
 	icepick_c_router $jrc 1 0x2 $port 0x2108
 
-	# Set 4 bit core ID to the Cortex-A
-	icepick_d_set_coreid $jrc $coreid
+	# Set icepick core control for $coreid
+	icepick_d_set_core_control $jrc $coreid $value
 
 	# Enter the bypass state
 	irscan $jrc [CONST IF_BYPASS] -endstate RUN/IDLE
diff --git a/tcl/target/imx51.cfg b/tcl/target/imx51.cfg
index d10cf9f..22af284 100644
--- a/tcl/target/imx51.cfg
+++ b/tcl/target/imx51.cfg
@@ -13,11 +13,11 @@ if { [info exists DAP_TAPID] } {
    set _DAP_TAPID 0x1ba00477
 }
 
-jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
         -expected-id $_DAP_TAPID
 
 # SDMA / no IDCODE
-jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf
+jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf
 
 # SJC
 if { [info exists SJC_TAPID] } {
@@ -26,15 +26,16 @@ if { [info exists SJC_TAPID] } {
    set _SJC_TAPID 0x0190c01d
 }
 
-jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
+jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \
         -expected-id $_SJC_TAPID -ignore-version
 
 # GDB target: Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
 
 # some TCK tycles are required to activate the DEBUG power domain
-jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
+jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
 
 proc imx51_dbginit {target} {
      # General Cortex-A8 debug initialisation
diff --git a/tcl/target/imx53.cfg b/tcl/target/imx53.cfg
index 5ad6473..84a85ba 100644
--- a/tcl/target/imx53.cfg
+++ b/tcl/target/imx53.cfg
@@ -13,11 +13,11 @@ if { [info exists DAP_TAPID] } {
    set _DAP_TAPID 0x1ba00477
 }
 
-jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
         -expected-id $_DAP_TAPID
 
 # SDMA / no IDCODE
-jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf
+jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf
 
 # SJC
 if { [info exists SJC_TAPID] } {
@@ -26,15 +26,16 @@ if { [info exists SJC_TAPID] } {
    set _SJC_TAPID 0x0190d01d
 }
 
-jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
+jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \
         -expected-id $_SJC_TAPID -ignore-version
 
 # GDB target: Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
 
 # some TCK tycles are required to activate the DEBUG power domain
-jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
+jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
 
 proc imx53_dbginit {target} {
      # General Cortex-A8 debug initialisation
diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg
index 4f7e98a..5b59ecf 100644
--- a/tcl/target/imx6.cfg
+++ b/tcl/target/imx6.cfg
@@ -13,7 +13,7 @@ if { [info exists DAP_TAPID] } {
         set _DAP_TAPID 0x4ba00477
 }
 
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
         -expected-id $_DAP_TAPID
 
 # SDMA / no IDCODE
@@ -40,7 +40,8 @@ jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
 # core 2  -  0x82154000
 # core 3  -  0x82156000
 set _TARGETNAME $_CHIPNAME.cpu.0
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
         -coreid 0 -dbgbase 0x82150000
 
 # some TCK cycles are required to activate the DEBUG power domain
diff --git a/tcl/target/imx7.cfg b/tcl/target/imx7.cfg
index d16e95a..f47dd7d 100644
--- a/tcl/target/imx7.cfg
+++ b/tcl/target/imx7.cfg
@@ -11,7 +11,7 @@ if { [info exists DAP_TAPID] } {
         set _DAP_TAPID 0x5ba00477
 }
 
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
         -expected-id $_DAP_TAPID
 
 #
@@ -22,16 +22,19 @@ jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
 # core 0  -  0x80070000
 # core 1  -  0x80072000
 set _TARGETNAME $_CHIPNAME.cpu_a7
-target create $_TARGETNAME.0 cortex_a -chain-position $_CHIPNAME.dap \
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap \
         -coreid 0 -dbgbase 0x80070000
 
-target create $_TARGETNAME.1 cortex_a -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap \
         -coreid 1 -dbgbase 0x80072000 -defer-examine
 #
 # Cortex-M4 target
 #
 set _TARGETNAME_2 $_CHIPNAME.cpu_m4
-target create $_TARGETNAME_2 cortex_m -chain-position $_CHIPNAME.dap -ap-num 4 \
+target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.dap -ap-num 4 \
         -defer-examine
 
 targets $_TARGETNAME.0
diff --git a/tcl/target/k1921vk01t.cfg b/tcl/target/k1921vk01t.cfg
index 61b193e..1a84021 100755
--- a/tcl/target/k1921vk01t.cfg
+++ b/tcl/target/k1921vk01t.cfg
@@ -31,9 +31,10 @@ if { [info exists CPUTAPID] } {
    }
 }
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/ke0x.cfg b/tcl/target/ke0x.cfg
index 1f1b132..8239400 100644
--- a/tcl/target/ke0x.cfg
+++ b/tcl/target/ke0x.cfg
@@ -25,9 +25,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/klx.cfg b/tcl/target/klx.cfg
index 1a2ee67..5d9286a 100644
--- a/tcl/target/klx.cfg
+++ b/tcl/target/klx.cfg
@@ -26,9 +26,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -43,7 +44,19 @@ adapter_khz 1000
 
 reset_config srst_nogate
 
-if {![using_hla]} {
+if {[using_hla]} {
+   echo ""
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo " Kinetis MCUs have a MDM-AP dedicated mainly to MCU security related functions."
+   echo " A high level adapter (like a ST-Link) you are currently using cannot access"
+   echo " the MDM-AP, so commands like 'mdm mass_erase' are not available in your"
+   echo " configuration. Also security locked state of the device will not be reported."
+   echo ""
+   echo " Be very careful as you can lock the device though there is no way to unlock"
+   echo " it without mass erase. Don't set write protection on the first block."
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo ""
+} {
    # Detect secured MCU or boot lock-up in RESET/WDOG loop
    $_CHIPNAME.cpu configure -event examine-start {
       kinetis mdm check_security
diff --git a/tcl/target/kx.cfg b/tcl/target/kx.cfg
index 7b03517..73ee62a 100644
--- a/tcl/target/kx.cfg
+++ b/tcl/target/kx.cfg
@@ -30,9 +30,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -44,7 +45,20 @@ adapter_khz 1000
 
 reset_config srst_nogate
 
-if {![using_hla]} {
+if {[using_hla]} {
+   echo ""
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo " Kinetis MCUs have a MDM-AP dedicated mainly to MCU security related functions."
+   echo " A high level adapter (like a ST-Link) you are currently using cannot access"
+   echo " the MDM-AP, so commands like 'mdm mass_erase' are not available in your"
+   echo " configuration. Also security locked state of the device will not be reported."
+   echo " Expect problems connecting to a blank device without boot ROM."
+   echo ""
+   echo " Be very careful as you can lock the device though there is no way to unlock"
+   echo " it without mass erase. Don't set write protection on the first block."
+   echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
+   echo ""
+} {
    # Detect secured MCU or boot lock-up in RESET/WDOG loop
    $_CHIPNAME.cpu configure -event examine-start {
       kinetis mdm check_security
diff --git a/tcl/target/lpc1850.cfg b/tcl/target/lpc1850.cfg
index a781403..925a049 100644
--- a/tcl/target/lpc1850.cfg
+++ b/tcl/target/lpc1850.cfg
@@ -23,9 +23,10 @@ if { [info exists M3_JTAG_TAPID] } {
 }
 
 swj_newdap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.m3
 
 set _TARGETNAME $_CHIPNAME.m3
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg
index 9c10e9f..701adf2 100644
--- a/tcl/target/lpc1xxx.cfg
+++ b/tcl/target/lpc1xxx.cfg
@@ -75,9 +75,10 @@ if { [info exists WORKAREASIZE] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 # The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
 # The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg
index 4e23ffb..2b72884 100644
--- a/tcl/target/lpc4350.cfg
+++ b/tcl/target/lpc4350.cfg
@@ -43,12 +43,14 @@ if { [info exists M0_JTAG_TAPID] } {
 
 swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
 				-expected-id $_M4_TAPID
-target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
+dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
 
 if { [using_jtag] } {
 	swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
 				-expected-id $_M0_JTAG_TAPID
-	target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
+	dap create $_CHIPNAME.m0.dap -chain-position $_CHIPNAME.m0
+	target create $_CHIPNAME.m0 cortex_m -dap $_CHIPNAME.m0.dap
 }
 
 # LPC4350 has 96+32 KB SRAM
diff --git a/tcl/target/lpc4370.cfg b/tcl/target/lpc4370.cfg
index 67bff0a..1374ef2 100644
--- a/tcl/target/lpc4370.cfg
+++ b/tcl/target/lpc4370.cfg
@@ -47,8 +47,8 @@ if { [info exists M0_JTAG_TAPID] } {
 
 swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
 				-expected-id $_M4_TAPID
-
-target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
+dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
 
 # LPC4370 has 96+32 KB contiguous SRAM
 if { [info exists WORKAREASIZE] } {
@@ -65,8 +65,10 @@ if { [using_jtag] } {
 	jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \
 					-expected-id $_M0_JTAG_TAPID
 
-	target create $_CHIPNAME.m0app cortex_m -chain-position $_CHIPNAME.m0app
-	target create $_CHIPNAME.m0sub cortex_m -chain-position $_CHIPNAME.m0sub
+	dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app
+	dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub
+	target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap
+	target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap
 
 	# 32+8+32 KB SRAM
 	$_CHIPNAME.m0app configure -work-area-phys 0x10080000 \
diff --git a/tcl/target/marvell/88f37x0.cfg b/tcl/target/marvell/88f37x0.cfg
index dba7da2..5e75135 100644
--- a/tcl/target/marvell/88f37x0.cfg
+++ b/tcl/target/marvell/88f37x0.cfg
@@ -35,7 +35,8 @@ if { [info exists DAP_TAPID] } {
 }
 
 # declare the one JTAG tap to access the DAP
-swj_newdap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 # declare the main application cores
 set _TARGETNAME $_CHIPNAME.cpu
@@ -43,9 +44,11 @@ set _smp_command ""
 
 for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
 
+    cti create cti$_core -dap $_CHIPNAME.dap -ctibase [lindex $_ctis $_core] -ap-num 0
+
     set _command "target create ${_TARGETNAME}$_core aarch64 \
-                         -chain-position $_CHIPNAME.dap -coreid $_core \
-                         -ctibase [lindex $_ctis $_core]"
+                         -dap $_CHIPNAME.dap -coreid $_core \
+                         -cti cti$_core"
 
     if { $_core != 0 } {
         # non-boot core examination may fail
@@ -63,6 +66,6 @@ for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
 eval $_smp_command
 
 # declare the auxiliary Cortex-M3 core on AP #3
-target create ${_TARGETNAME}.m3 cortex_m -chain-position $_CHIPNAME.dap -ap-num 3 -defer-examine
+target create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
 
 targets ${_TARGETNAME}0
diff --git a/tcl/target/mdr32f9q2i.cfg b/tcl/target/mdr32f9q2i.cfg
index 804ac1a..6748102 100644
--- a/tcl/target/mdr32f9q2i.cfg
+++ b/tcl/target/mdr32f9q2i.cfg
@@ -34,9 +34,10 @@ if { [info exists CPUTAPID] } {
    }
 }
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg
index 280dd4f..4f24020 100644
--- a/tcl/target/nrf51.cfg
+++ b/tcl/target/nrf51.cfg
@@ -31,9 +31,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg
index e730175..c29adbd 100644
--- a/tcl/target/nrf52.cfg
+++ b/tcl/target/nrf52.cfg
@@ -25,9 +25,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 adapter_khz 1000
 
diff --git a/tcl/target/numicro.cfg b/tcl/target/numicro.cfg
index 13d9654..c42dfbc 100644
--- a/tcl/target/numicro.cfg
+++ b/tcl/target/numicro.cfg
@@ -28,8 +28,9 @@ if { [info exists WORKAREASIZE] } {
 
 # Debug Adapter Target Settings
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index c2929d1..078d7f2 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -20,9 +20,9 @@ if { [info exists DAP_TAPID] } {
 } else {
    set _DAP_TAPID 0x0b6d602f
 }
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
+jtag configure $_CHIPNAME.cpu -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 3"
 
 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
@@ -36,7 +36,8 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
 
 # GDB target: Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
 
 # SRAM: 64K at 0x4020.0000; use the first 16K
 $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg
index 6f3525a..6e3e78d 100644
--- a/tcl/target/omap4430.cfg
+++ b/tcl/target/omap4430.cfg
@@ -22,9 +22,9 @@ if { [info exists DAP_TAPID] } {
 	set _DAP_TAPID 0x3BA00477
 }
 
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
+jtag configure $_CHIPNAME.cpu -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 9"
 
 
@@ -37,14 +37,14 @@ if { [info exists M3_DAP_TAPID] } {
 	set _M3_DAP_TAPID 0x4BA00477
 }
 
-jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m31_dap -event tap-enable \
+jtag configure $_CHIPNAME.m31 -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 5"
 
-jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m30_dap -event tap-enable \
+jtag configure $_CHIPNAME.m30 -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 4"
 
 
@@ -93,8 +93,9 @@ set _TARGETNAME $_CHIPNAME.cpu
 set _coreid 0
 set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
 echo "Using dbgbase = [format 0x%x $_dbgbase]"
- 
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
   -coreid 0 -dbgbase $_dbgbase
 
 # SRAM: 56KiB at 0x4030.0000
@@ -104,15 +105,17 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
 #
 # M3 targets, separate TAP/DAP for each core
 #
-target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
-target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
+dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
+dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
+target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
 
 
 # Once the JRC is up, enable our TAPs
 jtag configure $_CHIPNAME.jrc -event setup "
-	jtag tapenable $_CHIPNAME.dap
-	jtag tapenable $_CHIPNAME.m30_dap
-	jtag tapenable $_CHIPNAME.m31_dap
+	jtag tapenable $_CHIPNAME.cpu
+	jtag tapenable $_CHIPNAME.m30
+	jtag tapenable $_CHIPNAME.m31
 "
 
 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
@@ -124,4 +127,3 @@ $_CHIPNAME.m31 configure -event reset-assert { }
 
 # Soft breakpoints don't currently work due to broken cache handling
 gdb_breakpoint_override hard
-
diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg
index 9c40e62..218eb64 100644
--- a/tcl/target/omap4460.cfg
+++ b/tcl/target/omap4460.cfg
@@ -22,9 +22,9 @@ if { [info exists DAP_TAPID] } {
 	set _DAP_TAPID 0x3BA00477
 }
 
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
+jtag configure $_CHIPNAME.cpu -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 9"
 
 
@@ -37,14 +37,14 @@ if { [info exists M3_DAP_TAPID] } {
 	set _M3_DAP_TAPID 0x4BA00477
 }
 
-jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m31_dap -event tap-enable \
+jtag configure $_CHIPNAME.m31 -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 5"
 
-jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m30_dap -event tap-enable \
+jtag configure $_CHIPNAME.m30 -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 4"
 
 
@@ -94,7 +94,8 @@ set _coreid 0
 set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
 echo "Using dbgbase = [format 0x%x $_dbgbase]"
 
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
   -coreid 0 -dbgbase $_dbgbase
 
 # SRAM: 56KiB at 0x4030.0000
@@ -104,15 +105,17 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
 #
 # M3 targets, separate TAP/DAP for each core
 #
-target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
-target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
+dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
+dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
+target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
 
 
 # Once the JRC is up, enable our TAPs
 jtag configure $_CHIPNAME.jrc -event setup "
-	jtag tapenable $_CHIPNAME.dap
-	jtag tapenable $_CHIPNAME.m30_dap
-	jtag tapenable $_CHIPNAME.m31_dap
+	jtag tapenable $_CHIPNAME.cpu
+	jtag tapenable $_CHIPNAME.m30
+	jtag tapenable $_CHIPNAME.m31
 "
 
 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
diff --git a/tcl/target/psoc4.cfg b/tcl/target/psoc4.cfg
index d443b01..eb51847 100644
--- a/tcl/target/psoc4.cfg
+++ b/tcl/target/psoc4.cfg
@@ -1,4 +1,4 @@
-# script for Cypress PSoC 41xx/42xx family
+# script for Cypress PSoC 4 devices
 
 #
 # PSoC 4 devices support SWD transports only.
@@ -26,9 +26,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -53,8 +54,14 @@ adapter_khz 1500
 # set in time frame 400 usec delayed about 1 msec from reset.
 #
 # OpenOCD have no standard way how to set TEST_MODE in specified time frame.
-# TEST_MODE flag is set before reset instead. It worked for tested chips
-# despite it is not guaranteed by specification.
+# As a workaround the TEST_MODE flag is set before reset instead.
+# It worked for the oldest family PSoC4100/4200 even though it is not guaranteed
+# by specification.
+#
+# Newer families like PSoC 4000, 4100M, 4200M, 4100L, 4200L and PSoC 4 BLE
+# clear TEST_MODE flag during device reset so workaround is not possible.
+# Use a KitProg adapter for theese devices or "reset halt" will not stop
+# before executing user code.
 #
 # 3) SWD cannot be connected during system initialization after reset.
 # This might be a reason for unconnecting ST-Link v2 when deasserting reset.
@@ -66,11 +73,34 @@ if {![using_hla]} {
    cortex_m reset_config sysresetreq
 }
 
+proc psoc4_get_family_id {} {
+	set err [catch "mem2array romtable_pid 32 0xF0000FE0 3"]
+	if { $err } {
+		return 0
+	}
+	if { [expr $romtable_pid(0) & 0xffffff00 ]
+	  || [expr $romtable_pid(1) & 0xffffff00 ]
+	  || [expr $romtable_pid(2) & 0xffffff00 ] } {
+		echo "Unexpected data in ROMTABLE"
+		return 0
+	}
+	set designer_id [expr (( $romtable_pid(1) & 0xf0 ) >> 4) | (( $romtable_pid(2) & 0xf ) << 4 ) ]
+	if { $designer_id != 0xb4 } {
+		echo [format "ROMTABLE Designer ID 0x%02x is not Cypress" $designer_id]
+		return 0
+	}
+	set family_id [expr ( $romtable_pid(0) & 0xff ) | (( $romtable_pid(1) & 0xf ) << 8 ) ]
+	return $family_id
+}
+
 proc ocd_process_reset_inner { MODE } {
-	if { 0 != [string compare psoc4.cpu [target names]] } {
-		return -code error "PSoC 4 reset can handle only one psoc4.cpu target";
+	global PSOC4_USE_ACQUIRE PSOC4_TEST_MODE_WORKAROUND
+	global _TARGETNAME
+
+	if { 0 != [string compare $_TARGETNAME [target names]] } {
+		return -code error "PSoC 4 reset can handle only one $_TARGETNAME target";
 	}
-	set t psoc4.cpu
+	set t $_TARGETNAME
 
 	# If this target must be halted...
 	set halt -1
@@ -87,17 +117,42 @@ proc ocd_process_reset_inner { MODE } {
 		return -code error "Invalid mode: $MODE, must be one of: halt, init, or run";
 	}
 
+	if { ! [info exists PSOC4_USE_ACQUIRE] } {
+		if { 0 == [string compare [adapter_name] kitprog ] } {
+			set PSOC4_USE_ACQUIRE 1
+		} else {
+			set PSOC4_USE_ACQUIRE 0
+		}
+	}
+	if { $PSOC4_USE_ACQUIRE } {
+		set PSOC4_TEST_MODE_WORKAROUND 0
+	} elseif { ! [info exists PSOC4_TEST_MODE_WORKAROUND] } {
+		if { [psoc4_get_family_id] == 0x93 } {
+			set PSOC4_TEST_MODE_WORKAROUND 1
+		} else {
+			set PSOC4_TEST_MODE_WORKAROUND 0
+		}
+	}
+
 	#$t invoke-event reset-start
 	$t invoke-event reset-assert-pre
 
-	set TEST_MODE 0x40030014
-	if { $halt == 1 } {
-		mww $TEST_MODE 0x80000000
+	if { $halt && $PSOC4_USE_ACQUIRE } {
+		catch { [adapter_name] acquire_psoc }
+		$t arp_examine
 	} else {
-		mww $TEST_MODE 0
+		if { $PSOC4_TEST_MODE_WORKAROUND } {
+			set TEST_MODE 0x40030014
+			if { $halt == 1 } {
+				catch { mww $TEST_MODE 0x80000000 }
+			} else {
+				catch { mww $TEST_MODE 0 }
+			}
+		}
+
+		$t arp_reset assert 0
 	}
 
-	$t arp_reset assert 0
 	$t invoke-event reset-assert-post
 	$t invoke-event reset-deassert-pre
 	if {![using_hla]} {	# workaround ST-Link v2 fails and forcing reconnect
@@ -127,7 +182,14 @@ proc ocd_process_reset_inner { MODE } {
 		set pc [ocd_reg pc]
 		regsub {pc[^:]*: } $pc "" pc
 		if { $pc < 0x10000000 || $pc > 0x1000ffff } {
-			return -code error [format "TARGET: %s - Not halted in system ROM, use 'reset_config none'" $t]
+			set hint ""
+			set family_id [psoc4_get_family_id]
+			if { $family_id == 0x93 } {
+				set hint ", use 'reset_config none'"
+			} elseif { $family_id > 0x93 } {
+				set hint ", use a KitProg adapter"
+			}
+			return -code error [format "TARGET: %s - Not halted in system ROM%s" $t $hint]
 		}
 
 		# Set registers to reset vector values
@@ -135,7 +197,9 @@ proc ocd_process_reset_inner { MODE } {
 		reg pc [expr $value(1) & 0xfffffffe ]
 		reg msp $value(0)
 
-		mww $TEST_MODE 0
+		if { $PSOC4_TEST_MODE_WORKAROUND } {
+			catch { mww $TEST_MODE 0 }
+		}
 	}
 
 	#Pass 2 - if needed "init"
diff --git a/tcl/target/psoc5lp.cfg b/tcl/target/psoc5lp.cfg
index 1cdde47..230ca07 100644
--- a/tcl/target/psoc5lp.cfg
+++ b/tcl/target/psoc5lp.cfg
@@ -23,9 +23,10 @@ if { [using_jtag] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_DAP_ID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 if {![using_hla]} {
 	cortex_m reset_config sysresetreq
diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg
new file mode 100644
index 0000000..ad9aba5
--- /dev/null
+++ b/tcl/target/psoc6.cfg
@@ -0,0 +1,135 @@
+#
+# Configuration script for Cypress PSoC6 family of microcontrollers (CY8C6xxx)
+# PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
+# the same Flash/RAM/MMIO address space.
+#
+
+source [find target/swj-dp.tcl]
+
+adapter_khz 1000
+
+global _CHIPNAME
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME psoc6
+}
+
+global TARGET
+set TARGET $_CHIPNAME.cpu
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Is CM0 Debugging enabled ?
+global _ENABLE_CM0
+if { [info exists ENABLE_CM0] } {
+	set _ENABLE_CM0 $ENABLE_CM0
+} else {
+	set _ENABLE_CM0 1
+}
+
+# Is CM4 Debugging enabled ?
+global _ENABLE_CM4
+if { [info exists ENABLE_CM4] } {
+	set _ENABLE_CM4 $ENABLE_CM4
+} else {
+	set _ENABLE_CM4 1
+}
+
+global _WORKAREASIZE_CM0
+if { [info exists WORKAREASIZE_CM0] } {
+	set _WORKAREASIZE_CM0 $WORKAREASIZE_CM0
+} else {
+	set _WORKAREASIZE_CM0 0x4000
+}
+
+global _WORKAREASIZE_CM4
+if { [info exists WORKAREASIZE_CM4] } {
+	set _WORKAREASIZE_CM4 $WORKAREASIZE_CM4
+} else {
+	set _WORKAREASIZE_CM4 0x4000
+}
+
+global _WORKAREAADDR_CM0
+if { [info exists WORKAREAADDR_CM0] } {
+	set _WORKAREAADDR_CM0 $WORKAREAADDR_CM0
+} else {
+	set _WORKAREAADDR_CM0 0x08000000
+}
+
+global _WORKAREAADDR_CM4
+if { [info exists WORKAREAADDR_CM4] } {
+	set _WORKAREAADDR_CM4 $WORKAREAADDR_CM4
+} else {
+	set _WORKAREAADDR_CM4 0x08000000
+}
+
+proc init_reset { mode } {
+	global RESET_MODE
+	set RESET_MODE $mode
+
+	if {[using_jtag]} {
+		jtag arp_init-reset
+	}
+}
+
+# Utility to make 'reset halt' work as reset;halt on a target
+# It does not prevent running code after reset
+proc psoc6_deassert_post { target } {
+	# PSoC6 cleared AP registers including TAR during reset
+	# Force examine to synchronize OpenOCD target status
+	$target arp_examine
+
+	global RESET_MODE
+	if { $RESET_MODE ne "run" } {
+		$target arp_poll
+		$target arp_poll
+		set st [$target curstate]
+		if { $st eq "reset" } {
+			# we assume running state follows
+			# if reset accidentally halts, waiting is useless
+			catch { $target arp_waitstate running 100 }
+			set st [$target curstate]
+		}
+		if { $st eq "running" } {
+			echo "$target: Ran after reset and before halt..."
+			$target arp_halt
+		}
+	}
+}
+
+if { $_ENABLE_CM0 } {
+	target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
+	${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0
+
+	flash bank main_flash_cm0		psoc6 0x10000000 0 0 0 ${TARGET}.cm0
+	flash bank work_flash_cm0		psoc6 0x14000000 0 0 0 ${TARGET}.cm0
+	flash bank super_flash_user_cm0	psoc6 0x16000800 0 0 0 ${TARGET}.cm0
+	flash bank super_flash_nar_cm0	psoc6 0x16001A00 0 0 0 ${TARGET}.cm0
+	flash bank super_flash_key_cm0	psoc6 0x16005A00 0 0 0 ${TARGET}.cm0
+	flash bank super_flash_toc2_cm0	psoc6 0x16007C00 0 0 0 ${TARGET}.cm0
+
+	${TARGET}.cm0 cortex_m reset_config sysresetreq
+	${TARGET}.cm0 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm0"
+}
+
+if { $_ENABLE_CM4 } {
+	target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
+	${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0
+
+	flash bank main_flash_cm4		psoc6 0x10000000 0 0 0 ${TARGET}.cm4
+	flash bank work_flash_cm4		psoc6 0x14000000 0 0 0 ${TARGET}.cm4
+	flash bank super_flash_user_cm4	psoc6 0x16000800 0 0 0 ${TARGET}.cm4
+	flash bank super_flash_nar_cm4	psoc6 0x16001A00 0 0 0 ${TARGET}.cm4
+	flash bank super_flash_key_cm4	psoc6 0x16005A00 0 0 0 ${TARGET}.cm4
+	flash bank super_flash_toc2_cm4	psoc6 0x16007C00 0 0 0 ${TARGET}.cm4
+
+	${TARGET}.cm4 cortex_m reset_config vectreset
+	${TARGET}.cm4 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm4"
+}
+
+if { $_ENABLE_CM0 } {
+	# Use CM0+ by default on dual-core devices
+	targets ${TARGET}.cm0
+}
diff --git a/tcl/target/renesas_s7g2.cfg b/tcl/target/renesas_s7g2.cfg
index a09377b..78fb3e8 100644
--- a/tcl/target/renesas_s7g2.cfg
+++ b/tcl/target/renesas_s7g2.cfg
@@ -29,9 +29,10 @@ if { [using_jtag] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 if { [info exists WORKAREASIZE] } {
 	set _WORKAREASIZE $WORKAREASIZE
diff --git a/tcl/target/sim3x.cfg b/tcl/target/sim3x.cfg
index f721f36..ed46a3b 100755
--- a/tcl/target/sim3x.cfg
+++ b/tcl/target/sim3x.cfg
@@ -38,9 +38,10 @@ if { [info exists WORKAREASIZE] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 
diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
index 4fe9939..7fffd2a 100644
--- a/tcl/target/stellaris.cfg
+++ b/tcl/target/stellaris.cfg
@@ -42,7 +42,8 @@ if { [info exists CPUTAPID] } {
 # ... even though SWD ignores all except TAPID, and
 # JTAG shouldn't need anything more then irlen. (and TAPID).
 swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
- 	-expected-id $_CPUTAPID -ignore-version
+    -expected-id $_CPUTAPID -ignore-version
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
@@ -52,7 +53,7 @@ if { [info exists WORKAREASIZE] } {
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 # 8K working area at base of ram, not backed up
 #
diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg
index 2b48cfc..b8c0de9 100644
--- a/tcl/target/stm32f0x.cfg
+++ b/tcl/target/stm32f0x.cfg
@@ -32,9 +32,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index 5a4c2fa..e0f6ede 100644
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -36,13 +36,14 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
    jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
index 44955d4..80f9274 100644
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -49,13 +49,14 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
 	jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index 0c8919f..86e9f59 100644
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -49,13 +49,14 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
    jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index 7a0af9f..73b1dc8 100644
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -36,13 +36,14 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
    jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
index 4065e2a..dc310da 100755
--- a/tcl/target/stm32f7x.cfg
+++ b/tcl/target/stm32f7x.cfg
@@ -36,13 +36,14 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
    jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 02dbed4..10477a5 100644
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -34,13 +34,14 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
  swj_newdap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg
index 417b282..ec5d546 100644
--- a/tcl/target/stm32l0.cfg
+++ b/tcl/target/stm32l0.cfg
@@ -37,9 +37,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg
index a8d6fdf..054fa9b 100644
--- a/tcl/target/stm32l1.cfg
+++ b/tcl/target/stm32l1.cfg
@@ -45,13 +45,14 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
    jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg
index ccee48e..496b47a 100644
--- a/tcl/target/stm32l4x.cfg
+++ b/tcl/target/stm32l4x.cfg
@@ -36,13 +36,14 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
    jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
diff --git a/tcl/target/stm32w108xx.cfg b/tcl/target/stm32w108xx.cfg
index d07afc4..3a83fd1 100644
--- a/tcl/target/stm32w108xx.cfg
+++ b/tcl/target/stm32w108xx.cfg
@@ -37,6 +37,7 @@ if { [info exists CPUTAPID] } {
 set _ENDIAN little
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
  if { [info exists BSTAPID] } {
@@ -53,7 +54,7 @@ if {[using_jtag]} {
 # Set Target
 #
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
 
diff --git a/tcl/target/ti_msp432p4xx.cfg b/tcl/target/ti_msp432p4xx.cfg
index 8600867..461b595 100644
--- a/tcl/target/ti_msp432p4xx.cfg
+++ b/tcl/target/ti_msp432p4xx.cfg
@@ -31,9 +31,10 @@ if { [using_jtag] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 if { [info exists WORKAREASIZE] } {
 	set _WORKAREASIZE $WORKAREASIZE
diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg
index 66fc075..7d8bfe3 100644
--- a/tcl/target/u8500.cfg
+++ b/tcl/target/u8500.cfg
@@ -167,11 +167,11 @@ if { [info exists CPUTAPID] } {
 } else {
 	set _CPUTAPID 0x4ba00477
 }
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_CPUTAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
-	"u8500_dapenable $_CHIPNAME.dap"
-jtag configure $_CHIPNAME.dap -event tap-disable \
-	"u8500_tapdisable $_CHIPNAME.dap 0xc0"
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_CPUTAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
+	"u8500_dapenable $_CHIPNAME.cpu"
+jtag configure $_CHIPNAME.cpu -event tap-disable \
+	"u8500_tapdisable $_CHIPNAME.cpu 0xc0"
 
 
 #CLTAPC TAP JRC equivalent
@@ -202,7 +202,9 @@ if { [info exists DAP_DBG2] } {
 	set _DAP_DBG2 0x801AA000 
 }
 
-target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME_1 cortex_a -dap $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
 
 $_TARGETNAME_1 configure -event gdb-attach {
 	halt
@@ -217,7 +219,7 @@ global _TARGETNAME_2
 set _TARGETNAME_2 $TARGETNAME_2
 }
 
-target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
+target create $_TARGETNAME_2 cortex_a -dap $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
 
 $_TARGETNAME_2 configure -event gdb-attach {
 	halt
diff --git a/tcl/target/vybrid_vf6xx.cfg b/tcl/target/vybrid_vf6xx.cfg
index 6ec4b35..a1202ef 100644
--- a/tcl/target/vybrid_vf6xx.cfg
+++ b/tcl/target/vybrid_vf6xx.cfg
@@ -29,8 +29,9 @@ if { [using_jtag] } {
 source [find target/swj-dp.tcl]
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_A5_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.cpu -dbgbase 0xc0088000
+target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap -dbgbase 0xc0088000
 
 adapter_khz 1000
diff --git a/tcl/target/xilinx_ultrascale.cfg b/tcl/target/xilinx_ultrascale.cfg
new file mode 100644
index 0000000..9056c97
--- /dev/null
+++ b/tcl/target/xilinx_ultrascale.cfg
@@ -0,0 +1,92 @@
+#
+# target configuration for
+# Xilinx UltraScale+
+#
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME uscale
+}
+
+#
+# DAP tap
+#
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    set _DAP_TAPID 0x5ba00477
+}
+
+jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+#
+# PS tap
+#
+if { [info exists PS_TAPID] } {
+    set _PS_TAPID $PS_TAPID
+} else {
+    set _PS_TAPID 0x04710093
+}
+
+set jtag_configured 0
+
+jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID
+
+jtag configure $_CHIPNAME.ps -event setup {
+    global _CHIPNAME
+    global jtag_configured
+
+    if { $jtag_configured == 0 } {
+        # add the DAP tap to the chain
+        # See https://forums.xilinx.com/t5/UltraScale-Architecture/JTAG-Chain-Configuration-for-Zynq-UltraScale-MPSoC/td-p/758924
+        irscan $_CHIPNAME.ps 0x824
+        drscan $_CHIPNAME.ps 32 0x00000003
+        runtest 100
+
+        # setup event will be re-entered through jtag arp_init
+        # break the recursion
+        set jtag_configured 1
+        # re-initialized the jtag chain
+        jtag arp_init
+    }
+}
+
+set _TARGETNAME $_CHIPNAME.a53
+set _CTINAME $_CHIPNAME.cti
+set _smp_command ""
+
+set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
+set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+set _cores 4
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+
+    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+        -ctibase [lindex $CTIBASE $_core]
+
+    set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
+        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
+
+    if { $_core != 0 } {
+        # non-boot core examination may fail
+        set _command "$_command -defer-examine"
+        set _smp_command "$_smp_command $_TARGETNAME.$_core"
+    } else {
+        # uncomment when "hawt" rtos is merged
+        #set _command "$_command -rtos hawt"
+        set _smp_command "target smp $_TARGETNAME.$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
+targets $_TARGETNAME.0
+
+proc core_up { args } {
+    global _TARGETNAME
+    foreach { core } [set args] {
+        $_TARGETNAME.$core arp_examine
+    }
+}
diff --git a/tcl/target/xmc1xxx.cfg b/tcl/target/xmc1xxx.cfg
index d3123c4..e693b59 100644
--- a/tcl/target/xmc1xxx.cfg
+++ b/tcl/target/xmc1xxx.cfg
@@ -20,9 +20,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_SWD_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
 
 if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
diff --git a/tcl/target/xmc4xxx.cfg b/tcl/target/xmc4xxx.cfg
index bc00777..e106d34 100644
--- a/tcl/target/xmc4xxx.cfg
+++ b/tcl/target/xmc4xxx.cfg
@@ -35,9 +35,10 @@ if { [using_jtag] } {
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 # Work-area is a space in RAM used for flash programming
 # By default use 16 kB
diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg
index 70a8616..07a6c83 100644
--- a/tcl/target/zynq_7000.cfg
+++ b/tcl/target/zynq_7000.cfg
@@ -13,11 +13,13 @@ jtag newtap zynq_pl bs -irlen 6 -ircapture 0x1 -irmask 0x03 \
     -expected-id 0x03727093 \
     -expected-id 0x03736093
 
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
 
-target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.dap \
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap \
     -coreid 0 -dbgbase 0x80090000
-target create ${_TARGETNAME}1 cortex_a -chain-position $_CHIPNAME.dap \
+target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \
     -coreid 1 -dbgbase 0x80092000
 target smp ${_TARGETNAME}0 ${_TARGETNAME}1