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2022-02-26cpld: altera-epm240: Increase adapter speedSean Anderson1-0/+4
According to the datasheet, the minimum clock period with Vccio1 = 1.5V (the lowest voltage supported) is 143ns, or around 6MHz. Set the default adapter speed to 5 MHz. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de Reviewed-on: https://review.openocd.org/c/openocd/+/6847 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-26cpld: altera-epm240: Add additional IDCODEsSean Anderson1-1/+14
This adds some additional IDCODEs from the datasheet. It also adds support for customizing the tap name. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I7cda10b92c229b61836c12cd9ca410de358ede2e Reviewed-on: https://review.openocd.org/c/openocd/+/6846 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-14Cadence virtual debug interface (vdebug) integrationJacek Wuwer8-0/+225
Change-Id: I1bc105b3addc3f34161c2356c482ff3011e3f2cc Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6097 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: zapb <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-01-29tcl/board: Add EVB-LAN9255 configHans-Erik Floryd1-0/+11
Config for EVB-LAN9255, tested using Atmel-ICE debugger on J10 connector. Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Change-Id: I8bcf779e9363499a98aa0b7d10819c53da6a19e7 Reviewed-on: https://review.openocd.org/c/openocd/+/6812 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-01-28Merge branch 'master' into from_upstreamTim Newsome1-0/+2
Change-Id: I61e24edbdeceddba265514fd7e0a489ec23e2a4c
2022-01-05flash/nor/efr32: fixed lockbits and user dataDoug Brunner1-0/+2
Changed flash driver to support writing to the user data page, as well as to any portion of the lockbits page above 512 bytes (the amount used for the actual page lock words). The top part of the lockbits page is used on at least the EFR32xG1 chips for the SiLabs bootloader encryption keys. As presented to the user, the lockbits page is the same size as the other pages, but any attempt to write to its low 512 bytes is an error. To enforce this, efr32x_write is renamed to efm32x_priv_write and a wrapper function is provided in its place. If the user erases the lockbits page, the driver rewrites the cached lock words after the erase. When the driver erases the lockbits page in order to update the lock words, it first takes a copy of anything stored in the top part of the page, and re-programs it after the erase operation. There are now multiple instances of flash_bank for each target, and the flash_bank instances must share their cached lock words to operate as intended. Therefore, when a bank is created, the global flash bank list is used to find any other banks that share the same target. Since some banks in the global list are invalid at the time free_driver_priv is called, reference counting is used to decide when to free driver_priv. To avoid the need to find the lockbits flash_bank from another flash_bank, efm32x_priv_write and efm32x_erase_page now take an absolute address. There didn't seem to be any reason to prohibit unprotecting individual flash pages, so that limitation is removed from efm32x_protect(). This addresses ticket #185. Valgrind-clean, except for 2x 4kiB not freed/still reachable blocks that were allocated by libudev. No new Clang analyzer warnings, no new sanitizer warnings. Signed-off-by: Doug Brunner <doug.a.brunner@gmail.com> Change-Id: Ifb22e6149939d893f386706e99b928691ec1d41b Reviewed-on: https://review.openocd.org/c/openocd/+/6665 Tested-by: jenkins Reviewed-by: Fredrik Hederstierna <fredrik.hederstierna@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-12-28Merge branch 'master' into from_upstreamTim Newsome3-0/+124
Conflicts: doc/openocd.texi src/flash/nor/fespi.c Change-Id: Iaac61cb6ab8bba9df1d4b9a52671a09163eb50b2
2021-12-14Handle changed `ftdi` syntax. (#670)Tim Newsome5-39/+39
Also rename ftdi_oscan1_mode command which only exists in our branch. Change-Id: Ie9b28f228b1fd984244edb8162d552104d28e462 Signed-off-by: Tim Newsome <tim@sifive.com>
2021-12-11Add Microchip SAME51 Curiosity Nano boardJoerg Wunsch1-0/+14
This board is (software wise) similar to the existing SAME54 Xplained Pro board, with just a slightly different MCU. (Hardware wise, it features a vastly different form factor.) Signed-off-by: Jörg Wunsch <openocd@uriah.heep.sax.de> Change-Id: I5e5435d49d333fb74471994ee84de59ed983153c Reviewed-on: https://review.openocd.org/c/openocd/+/6747 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Axel W. Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-12-03tcl: stm32mp13x: add target and board config filesAntonio Borneo2-0/+110
The stm32mp13x has one core Cortex-A7. The board Discovery Kit includes an on-board STLink-V3 with SWD connection. The webpage of the board is not active yet. Change-Id: I8836b26612a160ead79766955ebefaf3d21a329c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6675 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-11-30Merge branch 'master' into from_upstreamTim Newsome10-9/+83
Merged 1ad6ed38b6da09b1d5d9e56d1344fced2dce12bc Conflicts: src/rtos/rtos_standard_stackings.c Change-Id: Ica8109135de0f9aa87455353a4538b161b844b04
2021-11-28jtag/hla, jtag/stlink: switch to command 'adapter serial'Antonio Borneo3-3/+3
The driver hla defines the command 'hla_serial' to specify the serial string of the adapter. The driver st-link defines the command 'st-link serial' to specify the serial string of the adapter. Remove and deprecate the driver commands and use 'adapter serial'. Change-Id: I9505c398a77125b1ebf4ba71da7baf4d663b75be Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6657 Tested-by: jenkins
2021-11-28jtag/jlink: switch to command 'adapter serial'Antonio Borneo1-1/+1
The driver jlink defines the command 'jlink serial' to specify the serial string of the adapter. Remove and deprecate the driver command, and use 'adapter serial'. Note: in former code the commands 'jlink serial' and 'jlink usb' were mutually exclusive; running one of them would invalidate the effect of a previous execution of the other. The new code gives priority to 'adapter serial', even if executed before 'jlink usb'. Change-Id: I920b0c136716f459b6fd6f7da8a01a7fa1ed389f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6656 Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2021-11-28jtag/xds110: switch to command 'adapter serial'Antonio Borneo1-1/+1
The driver xds110 defines the command 'xds110 serial' to specify the serial string of the adapter. Remove and deprecate the driver command, and use 'adapter serial'. Note: the original command 'xds110 serial' used a complex and undocumented conversion of the serial number through multibyte string, wide-character string and C cast. The XDS110 I can access and the lsusb dumps available through Google don't show any exotic USB serial that require such conversion. The original developer doesn't remember any constraint that mandates such conversion (see comments in https://review.openocd.org/4322/). The conversion is removed by this patch. Change-Id: I38909918079b2c1797ad85ebec2fea1b33743606 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6655 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2021-11-28jtag/kitprog: switch to command 'adapter serial'Antonio Borneo1-1/+1
The driver kitprog defines the command 'kitprog_serial' to specify the serial string of the adapter. Remove and deprecate the driver command, and use 'adapter serial'. Change-Id: I844cb815af01137392b6d12e1b5972fc77ac092d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6652 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2021-11-28jtag/ftdi: switch to command 'adapter serial'Antonio Borneo1-1/+1
The driver ftdi defines the command 'ftdi serial' to specify the serial string of the adapter. Remove and deprecate the driver command, and use 'adapter serial'. Change-Id: Ia5b1f325b9fab8f58b5ea70f8b807e50b148b939 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6651 Tested-by: jenkins
2021-11-28jtag/cmsis_dap: switch to command 'adapter serial'Antonio Borneo1-1/+1
The driver cmsis_dap defines the command 'cmsis_dap_serial' to specify the serial string of the adapter. Remove and deprecate the driver command, and use 'adapter serial'. Change-Id: I88e2d4de360a6c6f23529bb18494962a267250df Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6649 Tested-by: jenkins
2021-11-28jtag/aice: switch to command 'adapter serial'Antonio Borneo1-1/+1
The driver aice defines the command 'aice serial' to specify the serial string of the adapter, but actually does not use this value in the code. Remove and deprecate the driver command, and use 'adapter serial'. Change-Id: I892e0a4e1b41a7a87adf54a5736abf7419f32979 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6648 Tested-by: jenkins
2021-11-15flash/nor/stm32f1x: Add support for GD32E23xasier701-0/+74
GD32E23x from GigaDevice is cortex-M23 microcontroller and it can work with the stm32f1x driver. Modifications are similar to this done for GD32F1x0 in #6164 (https://review.openocd.org/c/openocd/+/6164). Configuration file is added because its cortex-M23 CPU ID is different. I think that GigaDevice microcontrollers should be handled in an independent unit to separate them from STM32, but nowadays quick solution is welcome. Signed-off-by: asier70Andrzej Sierżęga <asier70@gmail.com> Change-Id: I91f31f5f66808bc50a8f607ac2c107e6b7c5e2b8 Reviewed-on: https://review.openocd.org/c/openocd/+/6527 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-10-25Merge branch 'master' into from_upstreamTim Newsome1-1/+4
This primarily contains the large upstreaming of RISC-V changes, so lots more RISC-V changes than usual. Conflicts: src/target/riscv/opcodes.h src/target/riscv/riscv-011.c src/target/riscv/riscv-013.c src/target/riscv/riscv.c src/target/riscv/riscv.h Change-Id: I1145dad538a5470ad209848572e6b0f560b671e9 Signed-off-by: Tim Newsome <tim@sifive.com>
2021-10-25tcl/stm32mp15x: freeze watchdog, recover SWD after power cycleAntonio Borneo1-1/+4
Freeze the IWDG watchdog when cores are halted to prevent a reset while debugging. The PMIC present on some board senses the nsrst and forces a power cycle to the target. The power cycle causes the SWJ-DP to restart in JTAG mode. If the debugger is using SWD, the mismatch triggers an error after the reset command. Ignore the error detected by 'dap init' and proceed executing the handler. The error in 'dap init' will force a reconnect during the following 'dap apid', restoring the SWD functionality. Change-Id: I04fcda6a5b8a1b080ab4e8890ecd0754d5ed12d9 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6599 Tested-by: jenkins
2021-10-05Merge branch 'master' into from_upstreamTim Newsome20-6/+123
Conflicts: src/jtag/drivers/remote_bitbang.c src/rtos/rtos_standard_stackings.c src/rtos/rtos_standard_stackings.h src/target/breakpoints.c src/target/riscv/riscv.c src/target/target.c Change-Id: Ia6fcba3d43be8ea31728f3bcc2be6cb7e3ccc5c5
2021-09-25tcl/stm32wlx.cfg: comply with new jimtcl expr syntaxTarek BOCHKATI1-1/+1
Change-Id: I2e9fd528817b14396c7643801aeea5c8dde668e0 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6557 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2021-09-18stlink: Add PID for V3 device without MSDAndreas Sandberg2-2/+2
Add the 0x3754 PID used by some STLINK-V3 devices when MSD has been disabled. This PID has been observed on a Nucleo-G431RB board. Signed-off-by: Andreas Sandberg <andreas@sandberg.uk> Change-Id: Idb85874fa5a9dff5940bae7e95426a956693b976 Reviewed-on: https://review.openocd.org/c/openocd/+/6555 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-09-17tcl/target/stm32(f7/h7)x: do not assume presence of the resetTarek BOCHKATI12-2/+22
do not force the presence of the reset line, since some custom boards may do not contain the reset line. Change-Id: I031ab34012b34a1b49def9db16461f9de0ae29cc Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reported-by: Fleck <fleckz@users.sourceforge.net> Fixes: https://sourceforge.net/p/openocd/tickets/316/ Reviewed-on: https://review.openocd.org/c/openocd/+/6506 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2021-09-04tcl/board: add st_nucleo_g4.cfg to cover known STM32G4 NUCLEO boardsTarek BOCHKATI1-0/+19
known boards are NUCLEO-G431KB, NUCLEO-G431RB and NUCLEO-G474RE note: this work safely with B-G431B-ESC1, B-G474E-DPOW1, STM32G474E-EVAL and STM32G484E-EVAL Change-Id: I132a97e1816620b182983edc8a4b272b52b9241d Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5484 Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2021-09-04tcl/board: add st_nucleo_g0.cfg to cover known STM32G0 NUCLEO boardsTarek BOCHKATI1-0/+19
known boards are NUCLEO-G031K8, NUCLEO-G070RB, NUCLEO-G071RB note: this work safely with STM32G0316-DISCO, STM32G071B-DISCO and STM32G081B-EVAL Change-Id: I483b6f44409228cd8c2c97b3c560927d1645c517 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5483 Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2021-09-04tcl/board/arty_s7: Fix proc and chip nameMarc Schink1-1/+1
Tested with Digilent Arty S7 board. Change-Id: I064f3b6537ae8d765d7f380ad53b922d584fdbe7 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/6509 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-09-02flash/nor: add support for Nuvoton NPCX series flashWealian Liao2-0/+59
Added NPCX flash driver to support the Nuvoton NPCX series microcontrollers. Add config file for NPCX series. Change-Id: Ia10b019a3521f59ad1e10ccdc56827ba30c3eac8 Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com> Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5950 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-08-30Merge branch 'master' into from_upstreamTim Newsome129-590/+1215
Conflicts: src/flash/nor/fespi.c src/jtag/drivers/ftdi.c src/rtos/FreeRTOS.c src/rtos/hwthread.c src/rtos/rtos.c src/rtos/rtos.h src/rtos/rtos_ecos_stackings.c src/rtos/rtos_embkernel_stackings.c src/rtos/rtos_standard_stackings.c src/rtos/rtos_standard_stackings.h src/rtos/rtos_ucos_iii_stackings.c src/server/gdb_server.c src/server/server.c src/target/riscv/riscv-013.c src/target/target.c src/target/target.h Change-Id: If0924a3e799260c33fae5feb85975b1273b45a0f
2021-08-30flash/stm32l4x: add support of STM32U57x/U58xTarek BOCHKATI1-0/+207
this device flash registers are quite similar to STM32L5 with this changes : - flash size is up to 2MB - 2MB variants are always dual bank - 1MB and 512KB variants could be dual bank (contiguous addressing) depending on DUALBANK bit(21) - flash data width is 16 bytes (quad-word) Change-Id: Id13c552270ce1071479ad418526e8a39ebe83cb1 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6108 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-08-26Update gd32vf103.cfg (#640)Robbert1-0/+3
After compiling OpenOCD from source (commit: 6edf98db7), OpenOCD could not connect with the target board which is a GD32VF103T_START development board, when I used the command: openocd -f "interface/cmsis-dap.cfg" -f "target/gd32vf103.cfg" Issue 1: The clock speed hasn't been set, the error message given is: Error: CMSIS-DAP command CMD_DAP_SWJ_CLOCK failed. Which can be solved by adding a clock speed setting to the gd32vf103.cfg file: adapter speed 1000 Issue 2: The default transport is not set to jtag, which it requires, the error shown is: Open On-Chip Debugger 0.11.0+dev-01861-g6edf98db7-dirty (2021-08-25-10:18) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'. embedded:startup.tcl:128: Error: session transport is "swd" but your config requires JTAG in procedure 'script' at file "embedded:startup.tcl", line 26 in procedure 'jtag' called at file "/home/user/riscv-openocd-tool/usr/local/bin/../share/openocd/scripts/target/gd32vf103.cfg", line 9 in procedure 'default_to_jtag' called at file "embedded:startup.tcl", line 133 at file "embedded:startup.tcl", line 128 This issue can be solved by adding the line: transport select jtag After adding these two lines, OpenOCD could connect to the development board successfully. Programming the flash also works.
2021-08-26flash/stm32l4x: add support of STM32WL5x dual coreTarek BOCHKATI1-28/+115
according the RM0453, the second core have a different Flash CR and SR registers for flash operations (called C2CR and C2SR). so we need to a different flash_regs than older L4 devices. @see stm32wl_cpu2_flash_regs the C2CR register don't contain LOCK and OPTLOCK bits, and this explain the addition of new register index called STM32_FLASH_CR_WLK_INDEX to look-up the CR with lock, to be used in locking/unlocking the flash. note: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1, to solve this read the UID64 (IEEE 64-bit unique device ID register) Change-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6050 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-08-26flash/stm32l4x: STM32L5 support programming when TZEN=1 and RDP=0x55Tarek BOCHKATI1-1/+5
when RDP level is 0.5 the provided work-area should reside in non-secure RAM to ensure that: - add a hint in the driver level - reduce the usage of secure RAM only when TZEN=1 and RDP is not 0.5 (check the target configuration file) Change-Id: Idbf2325e609b84ef8480eefdb49a176fdf7e07c7 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6035 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: jenkins
2021-08-26flash/stm32l4x: STM32L5 support programming when TZEN=1 and RDP=0xAATarek BOCHKATI1-12/+77
STM32L5 flash memory is aliased to 0x0C000000, this address mapping is used for secure applications. (0x08000000 for non-secure) this change allows the programming of secure and non-secure flash when trustzone is enabled and RDP level is 0 Change-Id: I89d1f1b5d493cf01a142ca4dbfef5a3731cab96e Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5936 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-08-25tcl: add lattice ECP5 family supportOleksij Rempel5-0/+112
Add support for ECP5 FPGA targets and board based on this chips: Radiona ULX3S and Lambdaconcept ECPIX-5 Change-Id: I932fc6e2458cda7d63ac21579acddea5b53410bc Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-on: https://review.openocd.org/c/openocd/+/6112 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-08-14tcl/interface: add Ashling Opella-LD FTDI config filesRanjith Chandran2-0/+39
Adding Ashling's FTDI based Debug adapter Opella-LD's JTAG and SWD config files Change-Id: Ie0e82e3b8326de37641901f5c825372cab31de58 Signed-off-by: ranjith.tc@ashling.com Reviewed-on: http://openocd.zylin.com/6379 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-08-14tcl: Adapt config files to new usb_blaster command syntaxMarc Schink5-12/+12
Change-Id: I4eb645f74ef31fc0b5882299b3487020aa142dd8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6408 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-08-14tcl/interface/buspirate: Adapt to new buspirate command syntaxMarc Schink1-5/+5
Change-Id: I1a82608532f043054abd22eb5b50ab5c5f58cee4 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6405 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-08-14tcl/interface: Adapt config files to new sysfsgpio command syntaxMarc Schink2-5/+5
Change-Id: I8e8dee6e8869d2853a7a73c8d4dc8b4891fb0389 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6403 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-08-14tcl/interface/dln-2-gpiod: Adapt to new linuxgpiod command syntaxMarc Schink1-6/+6
Change-Id: Ife1e52fe5da0e0374a606072f1faf7c598cf0e2b Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6401 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-08-14tcl/interface/jtag_vpi: Adapt to new jtag_vpi command syntaxMarc Schink1-2/+2
Change-Id: I27eeab5e3dd554af00799104471ee8f30fbd0c51 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6399 Tested-by: jenkins Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-08-14tcl/interface: Adapt config files to new bcm2835gpio command syntaxMarc Schink2-14/+14
Change-Id: I2d649117aa8dbdf5484ace068785a1416efa3ecc Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6397 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-08-14tcl/interface/jtag_dpi: Adapt to new jtag_dpi command syntaxMarc Schink1-2/+2
Change-Id: Icebf6f0a037f4ea9fb450581fcc599417bffc153 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6395 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-08-14tcl/interface/openjtag: Adapt to new openjtag command syntaxMarc Schink1-1/+1
Change-Id: I3a9d649dd38a913b1ce6d4a2d506bbf44743d529 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6388 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-08-14tcl/interface: Adapt config files to new parport command syntaxMarc Schink4-7/+7
Change-Id: Iffe7a04c36c6ec680497081a99d55b8c69f8f079 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6386 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-08-14add config for Microchip SAMA5D27 SOM1 Kit1Oleksij Rempel2-0/+47
... and related SAMA5D27 SoC. Change-Id: Ic2584e3005ac691642dc2e5a8ee3fb8a4eacaa00 Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-on: http://openocd.zylin.com/5275 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2021-07-31tcl/board: Add Raspberry Pi 4 model B boardJian-Hong Pan1-0/+13
OpenOCD cannot connect to BCM2711's JTAG interface on RPi 4B board until the reset configuration mode is set as trst_only. According to Table 94. GPIO Pins Alternative Function Assignment of Broadcom's BCM2711 ARM Peripherals datasheet [1] and Raspberry Pi's GPIO control in config.txt document [2], only Test Reset (TRST) pin (no System Reset, SRST) is exposed. [1] https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf [2] https://www.raspberrypi.org/documentation/configuration/config-txt/gpio.md Change-Id: I806f0be9700fa0f0944b42c8a651a5731adc762b Link: http://openocd.zylin.com/#/c/6364/1 Signed-off-by: Jian-Hong Pan <chienhung.pan@gmail.com> Reviewed-on: http://openocd.zylin.com/6367 Tested-by: jenkins Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-31tcl/board: Add Raspberry Pi 3 boardJian-Hong Pan1-0/+13
OpenOCD cannot connect to BCM2837's JTAG interface on RPi 3 board until the reset configuration mode is set as trst_only. According to Table 6-31 GPIO Pins Alternative Function Assignment of Broadcom's BCM2837 ARM Peripherials datasheet [1] and Raspberry Pi's GPIO control in config.txt document [2], only Test Reset (TRST) pin (no System Reset, SRST) is exposed. [1] https://usermanual.wiki/Datasheet/BCM2837ARMPeripheralsBroadcom.1054296467/view [2] https://www.raspberrypi.org/documentation/configuration/config-txt/gpio.md Change-Id: I26ff3924039ff7943faf0a5b1ad0427c8dbb88f2 Link: http://openocd.zylin.com/#/c/6364/1 Signed-off-by: Jian-Hong Pan <chienhung.pan@gmail.com> Reviewed-on: http://openocd.zylin.com/6366 Tested-by: jenkins Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-07-31interface/jtag_hat: Add interface configuration for the JTAG HATMatthew Mets1-0/+38
This adds support for the Blinkinlabs JTAG Hat, a Raspberry Pi expansion board that provides JTAG and SWD connections via level- shifting buffers. Change-Id: I228bf6a18890b7c3d6679bbc63bfe39f726d8323 Signed-off-by: Matthew Mets <matt@blinkinlabs.com> Reviewed-on: http://openocd.zylin.com/6372 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
generated by cgit v1.1 at 2025-09-19 10:18:39 +0000