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| author | Wealian Liao <WHLIAO@nuvoton.com> | 2020-11-26 10:25:09 +0800 |
|---|---|---|
| committer | Oleksij Rempel <linux@rempel-privat.de> | 2021-09-02 06:42:54 +0000 |
| commit | 385eedfc6f0b82c5d6715c740ee40bdce983ef04 (patch) | |
| tree | 8989d8f92b88dcddfcd76a9da5c56477a2b9c581 /tcl | |
| parent | a098816a6557e5882bf088ab12a06b94934f30ce (diff) | |
| download | riscv-openocd-385eedfc6f0b82c5d6715c740ee40bdce983ef04.zip riscv-openocd-385eedfc6f0b82c5d6715c740ee40bdce983ef04.tar.gz riscv-openocd-385eedfc6f0b82c5d6715c740ee40bdce983ef04.tar.bz2 | |
flash/nor: add support for Nuvoton NPCX series flash
Added NPCX flash driver to support the Nuvoton NPCX series
microcontrollers. Add config file for NPCX series.
Change-Id: Ia10b019a3521f59ad1e10ccdc56827ba30c3eac8
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5950
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/board/npcx_evb.cfg | 8 | ||||
| -rw-r--r-- | tcl/target/npcx.cfg | 51 |
2 files changed, 59 insertions, 0 deletions
diff --git a/tcl/board/npcx_evb.cfg b/tcl/board/npcx_evb.cfg new file mode 100644 index 0000000..4f28bc9 --- /dev/null +++ b/tcl/board/npcx_evb.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Nuvoton NPCX Evaluation Board + +source [find interface/jlink.cfg] +transport select swd + +source [find target/npcx.cfg] diff --git a/tcl/target/npcx.cfg b/tcl/target/npcx.cfg new file mode 100644 index 0000000..1a21e1f --- /dev/null +++ b/tcl/target/npcx.cfg @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for Nuvoton NPCX Cortex-M4 Series + +# Adapt based on what transport is active. +source [find target/swj-dp.tcl] + +# Set Chipname +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME NPCX_M4 +} + +# SWD DAP ID of Nuvoton NPCX Cortex-M4. +if { [info exists CPUDAPID ] } { + set _CPUDAPID $CPUDAPID +} else { + set _CPUDAPID 0x4BA00477 +} + +# Work-area is a space in RAM used for flash programming +# By default use 32kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +# Debug Adapter Target Settings +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# Initial JTAG/SWD speed +# For safety purposes, set for the lowest cpu clock configuration +# 4MHz / 6 = 666KHz, so use 600KHz for it +adapter speed 600 + +# For safety purposes, set for the lowest cpu clock configuration +$_TARGETNAME configure -event reset-start {adapter speed 600} + +# use sysresetreq to perform a system reset +cortex_m reset_config sysresetreq + +# flash configuration +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME |