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riscv-openocd.git
FE_402_fix
__archive__
add_macos_build
autoconf
bscan_optimization
bscan_tunnel
buf_sget
build32
busy
compliance_dev
debug-log-reg-failure
deinit
dmi_read
dmstatus_version
dsp5680_build
eclipse_memory_read
eclipse_multicore_fix
examine_command
examine_unavailable_harts
examine_unavailable_harts_backup
examine_unavailable_harts_rebase
examine_unavailable_harts_squash
fence_i_fix_for_release
fix-halt-reason-after-singlestep
fix_macbuild
gd32vf103
gdb_next_port
gitignore-build
global
halt_examine
haltreq
hypervisor_translate
jlink
log_output
macbuild
macro
manual_hwbp
master
mem64
mpsse_flush
multicore
new_bscan_approach
newprogram
nohartstatus
old_fixes_and_eclipse_memory_read
old_triggers
print_port
race
rbb_cleanup
regcache
regression_test_janmat_experim
release
remove-slot_t-from-riscv-013
reset_test
reverse-resume-order
riscv
riscv-batch-cleanup
riscv-compliance
riscv-compliance-dev
s2_increment
sba_tests
set_group
static
travis-nop
update_defines
us_xds110
vector2
winbuild
wip
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Age
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Author
Files
Lines
2017-07-06
Merge pull request #74 from riscv/build32
Tim Newsome
3
-7
/
+10
2017-07-03
Merge pull request #73 from riscv/old_triggers
Tim Newsome
1
-44
/
+130
2017-07-03
Merge pull request #69 from riscv/multi-gdb
Palmer Dabbelt
3
-43
/
+66
2017-07-03
Fix 32-bit build errors.
Tim Newsome
3
-7
/
+10
2017-07-03
Fix trigger set/clear bug.
Tim Newsome
1
-2
/
+2
2017-07-03
Add back support for type 1 triggers.
old_triggers
Tim Newsome
1
-42
/
+120
2017-07-01
Fix comment about saving the temporary register in examine procedure.
Dmitry Ryzhov
1
-2
/
+6
2017-06-30
Restore value of temporary register (s0) in examine OpenOCD procedure in case...
Dmitry Ryzhov
1
-0
/
+8
2017-06-27
Check for errors in read_csr().
Tim Newsome
1
-2
/
+10
2017-06-21
Don't set breakpoints on disabled harts
v20170621
Palmer Dabbelt
1
-0
/
+6
2017-06-21
No longer hard-code the non-RTOS hart to 0
Palmer Dabbelt
1
-3
/
+4
2017-06-21
Allow memory writes to proceed on all harts
Palmer Dabbelt
1
-6
/
+0
2017-06-21
Refactor examine, to avoid some assertions
Palmer Dabbelt
1
-9
/
+16
2017-06-21
Factor out checking if harts should be used
Palmer Dabbelt
3
-18
/
+35
2017-06-20
Set current_hartid from coreid
Palmer Dabbelt
3
-7
/
+5
2017-06-20
Set hardware triggers on all harts.
multicore
Tim Newsome
1
-33
/
+69
2017-06-20
Don't immediately segfault with -rtos on v0.11.
Tim Newsome
1
-0
/
+3
2017-06-20
Comment curious code.
Tim Newsome
1
-0
/
+4
2017-06-20
Update list of "threads" when harts are discovered.
Tim Newsome
3
-5
/
+13
2017-06-19
Put early DEBUG notice of XLEN back.
Tim Newsome
1
-0
/
+5
2017-06-16
Update debug_defines. Clarify debug output.
Tim Newsome
2
-52
/
+118
2017-06-16
Fix comment.
Tim Newsome
1
-1
/
+1
2017-06-16
Tell the user about detected harts.
Tim Newsome
1
-8
/
+10
2017-06-16
Tighten up debug output.
Tim Newsome
1
-17
/
+14
2017-06-15
Fix indentation to match OpenOCD style.
Tim Newsome
6
-335
/
+333
2017-06-15
Merge pull request #64 from riscv/release-fixes
Tim Newsome
2
-5
/
+12
2017-06-15
Fix print statements to work with 64-bit addresses
Tim Newsome
1
-4
/
+7
2017-06-15
Jump to the RTOS hartid after halting
Palmer Dabbelt
1
-0
/
+7
2017-06-15
Clear abstract errors from register_read_direct
Palmer Dabbelt
1
-5
/
+5
2017-06-15
Accept 64-bit addresses in CRC requests.
Tim Newsome
1
-1
/
+1
2017-06-13
Fix the build.
Tim Newsome
5
-77
/
+85
2017-06-13
Merge branch 'remotes/openocd/master' into riscv64
Tim Newsome
188
-8991
/
+15088
2017-06-08
Fix dmi_read() indentation; remove \n in LOG_ERROR
Tim Newsome
1
-25
/
+25
2017-06-07
riscv: Move the initialization of the field inside the structure for consistency
Megan Wachs
1
-5
/
+1
2017-06-07
riscv: v13 -- dmi_write must still check for the OP result
v20170608
Megan Wachs
1
-21
/
+17
2017-06-06
%p already includes 0x (on gcc)
Tim Newsome
1
-4
/
+4
2017-06-06
Don't leave fd undefined.
Tim Newsome
1
-1
/
+1
2017-06-02
flash: nor: ath79: fix build failure due to recent MIPS changes
Paul Fertser
1
-37
/
+35
2017-05-31
flash: Add support for Atheros (ath79) SPI interface
Tobias Diedrich
4
-0
/
+908
2017-05-31
imx_gpio: add mmap based jtag interface for IMX processors
Grzegorz Kostka
3
-2
/
+561
2017-05-25
Return 5 (SIGBREAK) not 2 (SIGINT) after a step
Palmer Dabbelt
1
-1
/
+1
2017-05-25
Pass EVENT_RESUMED in the RTOS
Palmer Dabbelt
1
-2
/
+3
2017-05-25
Invalidate the register cache when rtos_hartid==-1
Palmer Dabbelt
1
-1
/
+4
2017-05-25
Invalidate the register cache on step, resume, reset
Palmer Dabbelt
2
-0
/
+14
2017-05-22
riscv-v11: Don't perform unexpected operation in cache_write
Megan Wachs
1
-1
/
+1
2017-05-15
Check for abstractcs.busy, not just CMDERR_BUSY
Palmer Dabbelt
1
-0
/
+4
2017-05-15
Go back to 32-word read/write buffers
Palmer Dabbelt
1
-2
/
+2
2017-05-15
Don't re-read registers after they're written
Palmer Dabbelt
1
-8
/
+0
2017-05-15
Print out the actual CSR that's read
Palmer Dabbelt
1
-0
/
+1
2017-05-15
Build fixes
Palmer Dabbelt
2
-3
/
+3
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